ISSUE 9

Number 9
Category errata
Synopsis Please define truncation rules
State lrmdraft
Class errata-discuss
Arrival-DateJul 31 2001
Originator Paul Graham <pgraham@cadence.com>
Release 2001b: 4.6
Environment
Description
Having experimented with Verilog simulators, I have come to the conclusion
that truncation on the msb side occurs when an expression is assigned to a
smaller target. For instance:

wire [7:0] x = 16'habcd;

In this case, the 8 most significant bits are truncated from the expression,
and only 8'hcd is assigned to x.

Perhaps this behavior can be defined in the LRM, probably somewhere in
chapter 6.

Paul
Fix
Add a new 4.6 subsection with wording as follows:

4.6 Assignments and truncation

If the width of the right-hand side (RHS) expression is
larger than the width of the left-hand side (LHS) in an
assignment, the MSBs of the RHS expression will always
be discarded to match the size of the LHS. Implementations
are not required to warn or report any errors related to
assignment size-mismatch or truncation. Truncating the
sign bit of a signed expression may change the sign of the
result.

Example: 
    reg        [5:0] a;  
    reg signed [4:0] b;
 
    initial begin
      a = 8'hff; // After the assignment, a = 6'h3f
      b = 8'hff; // After the assignment, b = 5'h1f
    end
 
 Example:
    reg        [0:5] a;  
    reg signed [0:4] b, c;  

    initial begin
      a = 8'sh8f; // After the assignment, a = 6'h0f
      b = 8'sh8f; // After the assignment, b = 5'h0f
      c = -113;   // After the assignment, c = 15
    end
    // 1000_1111 = (-'h71 = -113) truncates to ('h0F = 15)
 
 Example:
    reg        [7:0] a;
    reg signed [7:0] b;  
    reg signed [5:0] c, d;

    initial begin
      a = 8'hff;
      c = a;      // After the assignment, c = 6'h3f
      b = -113;
      d = b;      // After the assignment, d = 6'h0f
    end

Audit-Trail
From: Shalom Bresticker <Shalom.Bresticker@motorola.com>
To: btf-bugs@boyd.com
Subject: Re: pending/9: Please define truncation rules
Date: Sun, 05 Aug 2001 15:40:23 +0300


I agree that it does not seem to be explicitly specified in the LRM
and it should be.

Other possible places for it are 4.5.3 and the "NOTE" in 9.2.

Shalom

 

Paul Graham wrote:
<blockquote TYPE=CITE>Having experimented with Verilog simulators, I have
come to the conclusion

that truncation on the msb side occurs when an expression is assigned
to a

smaller target.  For instance:

    wire [7:0] x = 16'habcd;

In this case, the 8 most significant bits are truncated from the expression,

and only 8'hcd is assigned to x.

Perhaps this behavior can be defined in the LRM, probably somewhere
in

chapter 6. 

-- 
 **************************************************************************
 Shalom Bresticker                           Shalom.Bresticker@motorola.com
 Motorola Semiconductor Israel, Ltd.                  Tel #: +972 9 9522268
 P.O.B. 2208, Herzlia 46120, ISRAEL                   Fax #: +972 9 9522890
 **************************************************************************

 


From: "Jayaram Bhasker" <JBhasker@eSilicon.com>
To: <Cliffc@sunburst-design.com>, <etf-bugs@boyd.com>
Cc:
Subject: RE: errata/9: PROPOSAL - Please define truncation rules
Date: Mon, 7 Apr 2003 12:26:49 -0400

Cliff:

>> If the width of the right-hand side (RHS) net or variable is smaller than the

I thnk you meant "larger", not "smaller".

Two comments:

1. The behavior for truncation should be same for numbers and variables. The
differences should be based solely on whether S is assigned to S or US, or
US is assigned to US or S.

2. On the last example (d=b), the explanation does not match the result. The
explanation says to preseve the sign bit (which I agree) but I dont see
it preseved for the value in d.

- bhasker

------
J. Bhasker, eSilicon Corp
1605 N. Cedar Crest Blvd, Ste 615, Allentown, PA 18104
jbhasker@esilicon.com, 610.439.6831, 610.770.9634(fax)



-----Original Message-----
From: Cliffc@sunburst-design.com [mailto:Cliffc@sunburst-design.com]
Sent: Monday, April 07, 2003 12:06 PM
To: etf-bugs@boyd.com
Subject: errata/9: PROPOSAL - Please define truncation rules


Precedence: bulk

6.3 Assignments of different sizes

If the width of the right-hand side (RHS) net or variable is smaller than the
width of the left-hand side (LHS) net or variable in a continuous assignment,
procedural assignment or continuous procedural assignment, the MSBs of the RHS
number, net or variable will always be truncated to match the size of the LHS
variable. Compliant Verilog simulators are not required to warn or report any
errors related to assignment size-mismatch or truncation. To simplify the
behavioral description for the remainder of section 6, "variable" will refer to
either a net or variable.

6.3.1 Assigning wider unsigned and signed numbers to variables

If a RHS unsigned number requires more bits than the LHS variable that is being assigned, the most significant bits of the RHS number will be truncated to force the RHS value to be of equal bit-width to the LHS variable. The truncated bits are lost for this assignment and the numeric value of the LHS number may not equal the pre-assignment RHS number.

Example:

reg [5:0] a;
reg signed [4:0] b;

initial begin
a = 8'hff; // After the assignment, a = 6'h3f
b = 8'hff; // After the assignment, b = 5'h1f
end

If a RHS signed number requires more bits than the LHS variable that is being assigned, the most significant bits, including the sign bit of the RHS number, will be truncated to force the RHS value to be of equal bit-width to the LHS variable. Truncating the sign bit may also change the polarity of the truncated value, the truncated bits are lost for this assignment and the numeric value of the LHS number may not equal the pre-assignment RHS number.

Example:

reg [5:0] a;
reg signed [4:0] b, c;

initial begin
a = 8'sh8f; // After the assignment, a = 6'h0f
b = 8'sh8f; // After the assignment, b = 5'h0f
c = -113; // After the assignment, c = 15
end
// 1000_1111 = (-'h71 = -113) truncates to ('h0F = 15)

6.3.2 Assigning wider variables to variables

If the RHS variable is an unsigned variable and is wider than the LHS variable that is being assigned, the most significant bits of the RHS variable will be truncated to force the RHS variable to be of equal width to the LHS variable. The truncated bits are lost for this assignment and the LHS variable value may not equal the pre-assignment RHS variable value.

Example:

reg [7:0] a;
reg signed [7:0] b;
reg signed [5:0] c, d;

initial begin
a = 8'hff;
c = a; // After the assignment, b = 6'h3f
b = -113;
d = b; // After the assignment, c = 6'h0f
end

If the RHS variable is a signed variable and is wider than the LHS variable that is being assigned, and if the LHS variable is a signed variable, the most significant bit of the larger RHS variable will become the most significant bit of the updated LHS variable and the most significant bits of the RHS variable will be truncated to force the RHS variable to be of equal width to the LHS variable. The truncated bits, including the replaced sign-bit of the RHS variable are lost for this assignment.

http://boydtechinc.com/cgi-bin/issueproposal.pl?cmd=view&pr=9

From: Shalom.Bresticker@motorola.com
To: "Clifford E. Cummings" <cliffc@sunburst-design.com>
Cc: etf-bugs@boyd.com
Subject: Re: errata/9: Modified proposal wording - truncation
Date: Wed, 9 Apr 2003 13:21:48 +0300 (IDT)

In last sentence, "Truncating the sign bit of a signed expression, may change
the sign of the result." there should be no comma after the word "expression".

Shalom


On Mon, 7 Apr 2003, Clifford E. Cummings wrote:

> Based on today's discussion, the ETF-9 proposal should be changed as shown
> below. Still outstanding is the "assignment" wording in the first paragraph
> and where this addition should be placed in the LRM. The attached PDF file
> is formatted and colorized.
>
> Blue - wording changes to the proposal made in today's meeting.
> Red - still seeking better wording.
>
> 6.3 Assignments of different sizes
> (perhaps should be a new section 4.6 instead of 6.3)
>
> If the width of the right-hand side (RHS) expression is larger than the
> width of the left-hand side (LHS) in a continuous assignment, procedural
> assignment or continuous procedural assignment, the MSBs of the RHS
> expression will always be discarded to match the size of the LHS. Compliant
> Verilog simulators are not required to warn or report any errors related to
> assignment size-mismatch or truncation. Truncating the sign bit of a signed
> expression, may change the sign of the result.
>
> (change wording to, "an assignment" ??)
>
> Example:
> reg [5:0] a; reg signed [4:0] b;
>
> initial begin
> a = 8'hff; // After the assignment, a = 6'h3f
> b = 8'hff; // After the assignment, b = 5'h1f
> end
>
> Example:
> reg [0:5] a; reg signed [0:4] b, c; initial begin a =
> 8'sh8f; // After the assignment, a = 6'h0f b = 8'sh8f; // After the
> assignment, b = 5'h0f
> c = -113; // After the assignment, c = 15
> end
> // 1000_1111 = (-'h71 = -113) truncates to ('h0F = 15)
>
> Example:
> reg [7:0] a; reg signed [7:0] b; reg signed [5:0] c,
> d; initial begin a = 8'hff; c = a; // After the assignment, c =
> 6'h3f b = -113;
> d = b; // After the assignment, d = 6'h0f
> end

From: "Clifford E. Cummings" <cliffc@sunburst-design.com>
To: etf-bugs@boyd.com
Subject: errata/9:PROPOSAL
Date: Sun, 19 Oct 2003 11:04:57 -0700

Hi, All -

Based previous ETF discussions, an updated ETF-9 proposal is shown below.

Regards - Cliff

PDF format can be found at
http://boydtechinc.com/etf/archive/att-2095/01-ETF_009_TruncationProposal20031020.PDF

Add a new 4.6 subsection with wording as follows:

4.6 Assignments and truncation

If the width of the right-hand side (RHS) expression is larger than the
width of the left-hand side (LHS) in an assignment, the MSBs of the RHS
expression will always be discarded to match the size of the LHS. Compliant
Verilog simulators are not required to warn or report any errors related to
assignment size-mismatch or truncation. Truncating the sign bit of a signed
expression, may change the sign of the result.

Example:
reg [5:0] a;
reg signed [4:0] b;

initial begin
a = 8'hff; // After the assignment, a = 6'h3f
b = 8'hff; // After the assignment, b = 5'h1f
end

Example:
reg [0:5] a;
reg signed [0:4] b, c;

initial begin
a = 8'sh8f; // After the assignment, a = 6'h0f
b = 8'sh8f; // After the assignment, b = 5'h0f
c = -113; // After the assignment, c = 15
end
// 1000_1111 = (-'h71 = -113) truncates to ('h0F = 15)

Example:
reg [7:0] a;
reg signed [7:0] b;
reg signed [5:0] c, d;

initial begin
a = 8'hff;
c = a; // After the assignment, c = 6'h3f
b = -113;
d = b; // After the assignment, d = 6'h0f
end

Fix replaced by Shalom.Bresticker@motorola.com on Thu Oct 30 04:53:51 2003
Cliff's updated proposal:

PDF format can be found at
http://boydtechinc.com/etf/archive/att-2095/01-ETF_009_TruncationProposal20031020.PDF


Add a new 4.6 subsection with wording as follows:

4.6 Assignments and truncation

If the width of the right-hand side (RHS) expression is larger than the
width of the left-hand side (LHS) in an assignment, the MSBs of the RHS
expression will always be discarded to match the size of the LHS. Compliant
Verilog simulators are not required to warn or report any errors related to
assignment size-mismatch or truncation. Truncating the sign bit of a signed
expression, may change the sign of the result.

Example: 
    reg        [5:0] a;  
    reg signed [4:0] b;
 
    initial begin
      a = 8'hff; // After the assignment, a = 6'h3f
      b = 8'hff; // After the assignment, b = 5'h1f
    end
 
 Example:
    reg        [0:5] a;  
    reg signed [0:4] b, c;  

    initial begin
      a = 8'sh8f; // After the assignment, a = 6'h0f
      b = 8'sh8f; // After the assignment, b = 5'h0f
      c = -113;   // After the assignment, c = 15
    end
    // 1000_1111 = (-'h71 = -113) truncates to ('h0F = 15)
 
 Example:
    reg        [7:0] a;
    reg signed [7:0] b;  
    reg signed [5:0] c, d;

    initial begin
      a = 8'hff;
      c = a;      // After the assignment, c = 6'h3f
      b = -113;
      d = b;      // After the assignment, d = 6'h0f
    end


From: Shalom Bresticker <Shalom.Bresticker@motorola.com>
To: etf-bugs@boyd.com
Cc:
Subject: Re: errata/9: PROPOSAL - Please define truncation rules (fwd)
Date: Thu, 30 Oct 2003 14:57:52 +0200

> Add a new 4.6 subsection with wording as follows:
>
> 4.6 Assignments and truncation
>
> If the width of the right-hand side (RHS) expression is larger than the
> width of the left-hand side (LHS) in an assignment, the MSBs of the RHS
> expression will always be discarded to match the size of the LHS. Compliant
> Verilog simulators are not required to warn or report any errors related to
> assignment size-mismatch or truncation. Truncating the sign bit of a signed
> expression, may change the sign of the result.

Should be no comma after the word "expression".

--
Shalom Bresticker Shalom.Bresticker@motorola.com
Design & Reuse Methodology Tel: +972 9 9522268
Motorola Semiconductor Israel, Ltd. Fax: +972 9 9522890
POB 2208, Herzlia 46120, ISRAEL Cell: +972 50 441478




Fix replaced by stefen@boyd.com on Mon Nov 3 14:53:41 2003
Add a new 4.6 subsection with wording as follows:

4.6 Assignments and truncation

If the width of the right-hand side (RHS) expression is
larger than the width of the left-hand side (LHS) in an
assignment, the MSBs of the RHS expression will always
be discarded to match the size of the LHS. Implementations
are not required to warn or report any errors related to
assignment size-mismatch or truncation. Truncating the
sign bit of a signed expression may change the sign of the
result.

Example: 
    reg        [5:0] a;  
    reg signed [4:0] b;
 
    initial begin
      a = 8'hff; // After the assignment, a = 6'h3f
      b = 8'hff; // After the assignment, b = 5'h1f
    end
 
 Example:
    reg        [0:5] a;  
    reg signed [0:4] b, c;  

    initial begin
      a = 8'sh8f; // After the assignment, a = 6'h0f
      b = 8'sh8f; // After the assignment, b = 5'h0f
      c = -113;   // After the assignment, c = 15
    end
    // 1000_1111 = (-'h71 = -113) truncates to ('h0F = 15)
 
 Example:
    reg        [7:0] a;
    reg signed [7:0] b;  
    reg signed [5:0] c, d;

    initial begin
      a = 8'hff;
      c = a;      // After the assignment, c = 6'h3f
      b = -113;
      d = b;      // After the assignment, d = 6'h0f
    end



Unformatted

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ETF_009_TruncationProposal20031020.PDF



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