| Add Proposal | Add Analysis | Edit Class, Environment, or Release |
| Number | 658
|
| Category | errata
|
| Synopsis | 14.5 Driving wired logic: error in Fig 14-6?
|
| State | open
|
| Class | duplicate
|
| Arrival-Date | Mar 13 2005
|
| Originator | Shalom.Bresticker@freescale.com
|
| Release | duplicate of 657
|
| Environment |
duplicate of 657 |
| Description |
I think there is an error in Figure 14-6. 14.5 says, "Module path output nets shall not have more than one driver within the module. Therefore, wired logic is not allowed at module path outputs." Figure 14-5 illustrates a violation of this wired-output rule." Figure 14-5(a) shows a diagram equivalent to the following: input e,f,g,h; output s; wand s; and (s,e,f); and (s,g,h); So module output s is driven by 2 AND gates. "In Figure 14-5(a), any module path to S is illegal because the path destination has two drivers." OK so far. "The example in Figure 14-6 is also illegal." Figure 14-6 shows a diagram essentially IDENTICAL to Figure 14-5(a), except in Figure 14-5(a), no name is given to the outputs of the individual AND gates whereas their combined, wired-together output is called S. In Figure 14-6, the individual AND gate outputs are called Q and R, and their wired-together combination, which is the module output, is unnamed. Note that in the Verilog description of the circuit of Figure 14-6, you can't give separate names to Q and R, because they are the same wire. So the names Q and R can't actually exist in the Verilog model. The text continues: "In this example, when the outputs Q and R are wired together, it creates a condition where both paths have multiple drivers from within the same module." Now this is very strange. First, as mentioned previously, this is the same diagram as Figure 14-5(a), why is it repeated? Second, Q and R are called outputs here, but they are not outputs of the module (although they are outputs of their corresponding gates). The language is suspicious. Third, you can't specify module delay paths to internal signals, only to module outputs, so you can't specify module paths which terminate in Q and R anyway. Fourth, the language, "when the outputs Q and R are wired together" is also suspicious. It implies that they might be wired together or not. But since the diagram shows them hard-wired together, there is no possibility of their being not wired together. Fifth, the text continues, "Although multiple output drivers to a path destination are prohibited inside the same module, they are allowed outside the module. The example in Figure 14-7 is legal since Q and R each have only one driver within the module in which the module paths are specified." Figure 14-7 has TWO significant changes from 14-6: Q and R are now in DIFFERENT modules, and they are wired together OUTSIDE the modules. The alternate Figure 14-6 I will present has only ONE significant difference from Figure 14-7, which also makes it more logical. Some of these questions might seem flimsy, but when I present what I think the figure should be, you will see that the language becomes much more understandable. In any case, at least the first and third questions above cause the text and figure to be strange. The text and figures are the same in 1364-1995, so the error already existed there. Since I suspected an error, I went to the Verilog-XL Reference manual (9/03 version). Lo and behold, instead of Figure 14-6 and its text, I find the following: "Illegal module paths: Two module path outputs with multiple output drivers" and a figure which shows Q and R as separate module outputs wired together OUTSIDE the module, not inside the module. Now the 1364 text becomes much more clear. 1. It is not the same diagram as 14-5(a), which also appears in the Verilog-XL LRM. 2. Q and R ARE module outputs. 3. Since Q and R are outputs, they can have module paths. 4. Since they are wired together outside the module, it depends how the module is instantiated. I can instantiate the module either connecting Q and R or not. 5. There is only one difference between this and Fig 14-7, that Q and R are now in spearate modules. I checked and Verilog-XL indeed does not allow you to specify module paths to Q and R if they are wired together outside the module. So in my opinion, Figure 14-6 should be as in the Verilog-XL LRM. However, the story does not end here. As I said, this goes back to 1364-1995 (and probably OVI), where the standard was strongly based on Verilog-XL, which was sort of a signoff reference. However, this same case, which the Verilog-XL LRM forbids, and the XL compiler does not allow, IS allowed by at least two of the newer simulators, NC-Verilog and VCS (I checked.) So what does the NCV LRM say? 'The IEEE 1364 standard states that "Module path output nets shall not have more than one driver within the module. Therefore, wired logic is not allowed at module path outputs." The specification shows the following two figures as examples of illegal module paths:" Here the NCV LRM shows the same figures as Fig 14-5(a) and Fig 14-6, which as mentioned, are essentially identical. The text continues: "The NC-Verilog simulator, unlike Verilog-XL, does not impose this restriction. You should remember, however, that this is a restriction in the language, and that if you use wired logic at module path outputs, you will not be able to simulate the module path delays with Verilog-XL." What is the bottom line? 1. I think the current Fig 14-6 is wrong. 2. The figure should be corrected or the restriction described by it should be deleted from the 1364 standard. One way or the other, it should not be left as it is. Shalom -- Shalom Bresticker Shalom.Bresticker @freescale.com Design & Verification Methodology Tel: +972 9 9522268 Freescale Semiconductor Israel, Ltd. Fax: +972 9 9522890 POB 2208, Herzlia 46120, ISRAEL Cell: +972 50 5441478 [ ]Freescale Internal Use Only [ ]Freescale Confidential Proprietary |
| Fix |
Unknown |
| Unformatted |
|
Hosted by Boyd Technology