| Edit Proposal | Edit Class, Environment, or Release |
| Number | 651
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| Category | errata
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| Synopsis | 14.2.4.2, Example 2: last => should be *>
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| State | proposal
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| Class | errata-simple
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| Arrival-Date | Feb 15 2005
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| Originator | Shalom Bresticker <Shalom.Bresticker@freescale.com>
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| Release | 2001b: 14.2.4.2
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| Description |
In 14.2.4.2, Example 2: module ALU (o1, i1, i2, opcode); input [7:0] i1, i2; input [2:1] opcode; output [7:0] o1; //functional description omitted specify // add operation if (opcode == 2'b00) (i1,i2 *> o1) = (25.0, 25.0); // pass-through i1 operation if (opcode == 2'b01) (i1 => o1) = (5.6, 8.0); // pass-through i2 operation if (opcode == 2'b10) (i2 => o1) = (5.6, 8.0); // delays on opcode changes (opcode => o1) = (6.1, 6.5); endspecify endmodule In the last delay specification, (opcode => o1) = (6.1, 6.5); the => (parallel path) should be *> (full path). => requires that the same size vector should be on both sides, input and output. Verilog-XL indeed flags a syntax error. Besides, the intent really is that each bit of opcode affects all of o1, which is what *> does. Shalom -- Shalom Bresticker Shalom.Bresticker @freescale.com Design & Verification Methodology Tel: +972 9 9522268 Freescale Semiconductor Israel, Ltd. Fax: +972 9 9522890 POB 2208, Herzlia 46120, ISRAEL Cell: +972 50 5441478 [ ]Freescale Internal Use Only [ ]Freescale Confidential Proprietary |
| Fix |
In 14.2.4.2, Example 2, CHANGE last => TO *> |
| Audit-Trail |
From: Shalom.Bresticker@freescale.com To: etf-bugs@boyd.com Cc: Subject: Re: errata/651: 14.2.4.2, Example 2: last => should be *> Date: Thu, 17 Feb 2005 11:03:21 +0200 (IST) I found in the Verilog-XL LRM that it is indeed "*>". So I will treat this as a clear typo and fix it in the ballot draft. > In the last delay specification, > > (opcode => o1) = (6.1, 6.5); > > the => (parallel path) should be *> (full path). Shalom Fix replaced by Shalom.Bresticker@freescale.com on Tue Feb 22 04:01:57 2005 In 14.2.4.2, Example 2, CHANGE last => TO *> |
| Unformatted |
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