| Add Proposal | Add Analysis | Edit Class, Environment, or Release |
| Number | 642
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| Category | errata
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| Synopsis | $swrite should overwrite entire string
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| State | open
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| Class | errata-simple
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| Arrival-Date | Dec 01 2004
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| Originator | Shalom.Bresticker@freescale.com
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| Release | 2001b
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| Description |
There seems to be an unclearness regarding $string. Suppose I write reg [4*8:1] msg ; begin $swrite (msg, "ABCD"); $swrite (msg, "EFG"); end After the 2nd $swrite, is the result " EFG" or "AEFG"? In my mind, it should be " EFG". But a certain tool overwrites only the right-hand characters of msg, according to the length of the string to be written, doing msg[n*8:1] = input_string ; where n = the length of input_string. So the LRM seems to require more explicit language. -- Shalom Bresticker Shalom.Bresticker @freescale.com Design & Verification Methodology Tel: +972 9 9522268 Freescale Semiconductor Israel, Ltd. Fax: +972 9 9522890 POB 2208, Herzlia 46120, ISRAEL Cell: +972 50 5441478 [ ]Freescale Internal Use Only [ ]Freescale Confidential Proprietary |
| Fix |
Unknown |
| Audit-Trail |
From: Steven Sharp <sharp@cadence.com> To: etf-bugs@boyd.com, Shalom.Bresticker@freescale.com Cc: Subject: errata/642: $swrite should overwrite entire string Date: Wed, 1 Dec 2004 17:44:38 -0500 (EST) I would think that the relevant text in 17.2.3 is: "The variable output_reg is assigned using the Verilog string assignment to variable rules, as specified in 4.2.3." That text was presumably put in to specify exactly what you are talking about. An assignment to the variable will replace the entire value, not overwrite part of it. If the value being assigned is narrower than the variable, it will be padded on the left with zeroes, as specified in 4.2.3. Seems pretty explicit to me. Steven Sharp sharp@cadence.com From: Shalom Bresticker <Shalom.Bresticker@freescale.com> To: Steven Sharp <sharp@cadence.com> Cc: etf-bugs@boyd.com Subject: Re: errata/642: $swrite should overwrite entire string Date: Thu, 02 Dec 2004 10:00:20 +0200 Apparently it was not explicit enough for someone. Shalom Steven Sharp wrote: > I would think that the relevant text in 17.2.3 is: > > "The variable output_reg is assigned using the Verilog string assignment > to variable rules, as specified in 4.2.3." > > That text was presumably put in to specify exactly what you are talking > about. An assignment to the variable will replace the entire value, > not overwrite part of it. If the value being assigned is narrower than > the variable, it will be padded on the left with zeroes, as specified > in 4.2.3. Seems pretty explicit to me. > > Steven Sharp > sharp@cadence.com -- Shalom Bresticker Shalom.Bresticker @freescale.com Design & Verification Methodology Tel: +972 9 9522268 Freescale Semiconductor Israel, Ltd. Fax: +972 9 9522890 POB 2208, Herzlia 46120, ISRAEL Cell: +972 50 5441478 [ ]Freescale Internal Use Only [ ]Freescale Confidential Proprietary From: Steven Sharp <sharp@cadence.com> To: etf-bugs@boyd.com, Shalom.Bresticker@freescale.com Cc: Subject: Re: errata/642: $swrite should overwrite entire string Date: Thu, 2 Dec 2004 13:55:41 -0500 (EST) > Apparently it was not explicit enough for someone. Or they failed to read the description carefully before implementing it, or accidentally implemented it wrong. I don't think we should assume it is the fault of the description, unless we find that someone actually read the description and still interpreted it incorrectly. Steven Sharp sharp@cadence.com From: Shalom.Bresticker@freescale.com To: Steven Sharp <sharp@cadence.com> Cc: etf-bugs@boyd.com Subject: Re: errata/642: $swrite should overwrite entire string Date: Thu, 2 Dec 2004 21:51:56 +0200 (IST) But there is no harm in making it more explicit. And it IS possible to make it more explicit. Shalom On Thu, 2 Dec 2004, Steven Sharp wrote: > > > Apparently it was not explicit enough for someone. > > Or they failed to read the description carefully before implementing it, > or accidentally implemented it wrong. I don't think we should assume it > is the fault of the description, unless we find that someone actually > read the description and still interpreted it incorrectly. > > Steven Sharp > sharp@cadence.com > -- Shalom Bresticker Shalom.Bresticker @freescale.com Design & Verification Methodology Tel: +972 9 9522268 Freescale Semiconductor Israel, Ltd. Fax: +972 9 9522890 POB 2208, Herzlia 46120, ISRAEL Cell: +972 50 5441478 [ ]Freescale Internal Use Only [ ]Freescale Confidential Proprietary |
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