| Number | 640
|
| Notify-List |
|
| Category | enhancement
|
| Synopsis | Add 'uwire' net type to enforce single-driver restriction
|
| State | lrmdraft
|
| Class | enhancement
|
| Arrival-Date | Nov 29 2004
|
| Originator | sharp
|
| Release |
|
| Environment |
|
| Description |
This enhancement request is for the already-passed uwire enhancement. I will attach the original proposal, and the passed proposal can be attached as a fix. |
| Fix |
-----------------------------------------------------------------------------
Annex A - A.2.2.2 and syntax box in 3.2.1:
CHANGE:
net_type ::=
supply0 | supply1
| tri | triand | trior | tri0 | tri1 | wire | wand | wor
TO:
net_type ::=
supply0 | supply1
| tri | triand | trior | tri0 | tri1 | uwire | wire | wand | wor
-----------------------------------------------------------------------------
3.7 Net types
In table 2, CHANGE:
| wor | trior | trireg | |
TO:
| wor | trior | trireg | uwire |
----------------------------------------------------------------------------
3.7 Net types
CHANGE:
3.7.5 Supply nets
TO:
3.7.6 Supply nets
ADD NEW SECTION 3.7.5:
3.7.5 Unresolved nets
The uwire net is an unresolved or unidriver wire, and is used to model
nets that allow only a single driver. The uwire type can be used to
enforce this restriction. It shall be an error to connect any bit of a
uwire net to more than one driver. It shall be an error to connect a
uwire net to a bidirectional terminal of a bidirectional pass switch.
The port connection rule in 12.3.9.3 ensures that an implementation
enforces this restriction across the net hierarchy, or gives a warning
if it does not.
----------------------------------------------------------------------------
3.12 Name spaces
CHANGE
"includes wire, wor, wand, tri, trior, triand, tri0, tri1, trireg, supply0,
and supply1"
TO
"includes wire, wor, wand, tri, trior, triand, tri0, tri1, trireg, uwire,
supply0, and supply1"
----------------------------------------------------------------------------
12.3.9 Port connection rules
ADD THIS SECTION:
12.3.9.3 Rule 3
If the net on either side of a port has the net type uwire,
a warning shall be issued if the nets are not merged into
a single net, as described in 12.3.10.
-----------------------------------------------------------------------------
12.3.10.2 Net type table
CHANGE:
---------------------------------------------------------------------
| External net
Internal |-----------------------------------------------------------
net |wire,|wand, |wor, |trireg | tri0 | tri1 |supply0 |supply1
| tri |triand |trior | | | | |
---------+-----+-------+------+-------+------+------+--------+---------
wire, | ext | ext | ext | ext | ext | ext | ext | ext
tri | | | | | | | |
---------+-----+-------+------+-------+-----+-----+--------+---------
wand, | int | ext | warn | warn | warn | warn | ext | ext
triand | | | | | | | |
---------+-----+-------+------+-------+------+------+--------+---------
wor, | int | warn | ext | warn | warn | warn | ext | ext
trior | | | | | | | |
---------+-----+-------+------+-------+-----+-----+--------+---------
trireg | int | warn | warn | ext | ext | ext | ext | ext
---------+-----+-------+------+-------+------+------+--------+---------
tri0 | int | warn | warn | int | ext | warn | ext | ext
---------+-----+-------+------+-------+------+------+--------+---------
tri1 | int | warn | warn | int | warn | ext | ext | ext
---------+-----+-------+------+-------+------+------+--------+---------
supply0 | int | int | int | int | int | int | ext | warn
---------+-----+-------+------+-------+--- --+------+--------+---------
supply1 | int | int | int | int | int | int | warn | ext
---------------------------------------------------------------------
KEY:
ext = The external net type is used
int = The internal net type is used
warn = A warning is issued and the external net type is used
--------------------------------------------------------------------------
TO:
----------------------------------------------------------------------------
| External net
Internal |------------------------------------------------------------------
net |wire,|wand, |wor, |trireg | tri0 | tri1 |uwire |supply0 |supply1
| tri |triand |trior | | | | | |
---------+-----+-------+------+-------+------+------+------+--------+-----
wire, | ext | ext | ext | ext | ext | ext | ext | ext | ext
tri | | | | | | | | |
---------+-----+-------+------+-------+------+------+------+--------+-----
wand, | int | ext | ext | ext | ext | ext | ext | ext | ext
triand | | | warn | warn | warn | warn | warn | |
---------+-----+-------+------+-------+------+------+------+--------+-----
wor, | int | ext | ext | ext | ext | ext | ext | ext | ext
trior | | warn | | warn | warn | warn | warn | |
---------+-----+-------+------+-------+------+------+------+--------+-----
trireg | int | ext | ext | ext | ext | ext | ext | ext | ext
| | warn | warn | | | | warn | |
---------+-----+-------+------+-------+------+------+------+--------+-----
tri0 | int | ext | ext | int | ext | ext | ext | ext | ext
| | warn | warn | | | warn | warn | |
---------+-----+-------+------+-------+------+------+------+--------+-----
tri1 | int | ext | ext | int | ext | ext | ext | ext | ext
| | warn | warn | | warn | | warn | |
---------+-----+-------+------+-------+------+------+------+--------+-----
uwire | int | int | int | int | int | int | ext | ext | ext
| | warn | warn | warn | warn | warn | | |
---------+-----+-------+------+-------+------+------+------+--------+-----
supply0 | int | int | int | int | int | int | int | ext | ext
| | | | | | | | | warn
---------+-----+-------+------+-------+------+------+------+--------+-----
supply1 | int | int | int | int | int | int | int | ext | ext
| | | | | | | | warn |
--------------------------------------------------------------------------
KEY:
ext = The external net type is used
int = The internal net type is used
warn = A warning is issued
----------------------------------------------------------------------------
----------------------------------------------------------------------------
19.2 `default_nettype
In Syntax 19-1, CHANGE
trior|trireg|none
TO
trior|trireg|uwire|none
----------------------------------------------------------------------------
18.2.3.8 $var
AFTER THE NUMBERED LIST, ADD THE FOLLOWING PARAGRAPH:
In the $var section, a net of net type uwire shall have a variable type
of wire.
----------------------------------------------------------------------------
Annex G: vpi_user.h
AFTER:
#define vpiNone 12 /* no default net type (1364-2000) */
ADD:
#define vpiUwire 13 /* unresolved wire net (1364-2005) */
----------------------------------------------------------------------------
Annex B
ADD "uwire" to list of keywords.
<\pre>
|
| Audit-Trail |
Fix replaced by sharp@cadence.com on Wed Dec 1 18:07:48 2004
-----------------------------------------------------------------------------
Annex A - A.2.2.2 and syntax box in 3.2.1:
CHANGE:
net_type ::=
supply0 | supply1
| tri | triand | trior | tri0 | tri1 | wire | wand | wor
TO:
net_type ::=
supply0 | supply1
| tri | triand | trior | tri0 | tri1 | uwire | wire | wand | wor
-----------------------------------------------------------------------------
3.7 Net types
In table 2, CHANGE:
| wor | trior | trireg | |
TO:
| wor | trior | trireg | uwire |
----------------------------------------------------------------------------
3.7 Net types
CHANGE:
3.7.5 Supply nets
TO:
3.7.6 Supply nets
ADD NEW SECTION 3.7.5:
3.7.5 Unresolved nets
The uwire net is an unresolved or unidriver wire, and is used to model
nets that allow only a single driver. The uwire type can be used to
enforce this restriction. It shall be an error to connect any bit of a
uwire net to more than one driver. It shall be an error to connect a
uwire net to a bidirectional terminal of a bidirectional pass switch.
The port connection rule in 12.3.9.3 ensures that an implementation
enforces this restriction across the net hierarchy, or gives a warning
if it does not.
----------------------------------------------------------------------------
3.12 Name spaces
CHANGE
"includes wire, wor, wand, tri, trior, triand, tri0, tri1, trireg, supply0,
and supply1"
TO
"includes wire, wor, wand, tri, trior, triand, tri0, tri1, trireg, uwire,
supply0, and supply1"
----------------------------------------------------------------------------
12.3.9 Port connection rules
ADD THIS SECTION:
12.3.9.3 Rule 3
If the net on either side of a port has the net type uwire,
a warning shall be issued if the nets are not merged into
a single net, as described in 12.3.10.
-----------------------------------------------------------------------------
12.3.10.2 Net type table
CHANGE:
---------------------------------------------------------------------
| External net
Internal |-----------------------------------------------------------
net |wire,|wand, |wor, |trireg | tri0 | tri1 |supply0 |supply1
| tri |triand |trior | | | | |
---------+-----+-------+------+-------+------+------+--------+---------
wire, | ext | ext | ext | ext | ext | ext | ext | ext
tri | | | | | | | |
---------+-----+-------+------+-------+-----+-----+--------+---------
wand, | int | ext | warn | warn | warn | warn | ext | ext
triand | | | | | | | |
---------+-----+-------+------+-------+------+------+--------+---------
wor, | int | warn | ext | warn | warn | warn | ext | ext
trior | | | | | | | |
---------+-----+-------+------+-------+-----+-----+--------+---------
trireg | int | warn | warn | ext | ext | ext | ext | ext
---------+-----+-------+------+-------+------+------+--------+---------
tri0 | int | warn | warn | int | ext | warn | ext | ext
---------+-----+-------+------+-------+------+------+--------+---------
tri1 | int | warn | warn | int | warn | ext | ext | ext
---------+-----+-------+------+-------+------+------+--------+---------
supply0 | int | int | int | int | int | int | ext | warn
---------+-----+-------+------+-------+--- --+------+--------+---------
supply1 | int | int | int | int | int | int | warn | ext
---------------------------------------------------------------------
KEY:
ext = The external net type is used
int = The internal net type is used
warn = A warning is issued and the external net type is used
--------------------------------------------------------------------------
TO:
----------------------------------------------------------------------------
| External net
Internal |------------------------------------------------------------------
net |wire,|wand, |wor, |trireg | tri0 | tri1 |uwire |supply0 |supply1
| tri |triand |trior | | | | | |
---------+-----+-------+------+-------+------+------+------+--------+-----
wire, | ext | ext | ext | ext | ext | ext | ext | ext | ext
tri | | | | | | | | |
---------+-----+-------+------+-------+------+------+------+--------+-----
wand, | int | ext | ext | ext | ext | ext | ext | ext | ext
triand | | | warn | warn | warn | warn | warn | |
---------+-----+-------+------+-------+------+------+------+--------+-----
wor, | int | ext | ext | ext | ext | ext | ext | ext | ext
trior | | warn | | warn | warn | warn | warn | |
---------+-----+-------+------+-------+------+------+------+--------+-----
trireg | int | ext | ext | ext | ext | ext | ext | ext | ext
| | warn | warn | | | | warn | |
---------+-----+-------+------+-------+------+------+------+--------+-----
tri0 | int | ext | ext | int | ext | ext | ext | ext | ext
| | warn | warn | | | warn | warn | |
---------+-----+-------+------+-------+------+------+------+--------+-----
tri1 | int | ext | ext | int | ext | ext | ext | ext | ext
| | warn | warn | | warn | | warn | |
---------+-----+-------+------+-------+------+------+------+--------+-----
uwire | int | int | int | int | int | int | ext | ext | ext
| | warn | warn | warn | warn | warn | | |
---------+-----+-------+------+-------+------+------+------+--------+-----
supply0 | int | int | int | int | int | int | int | ext | ext
| | | | | | | | | warn
---------+-----+-------+------+-------+------+------+------+--------+-----
supply1 | int | int | int | int | int | int | int | ext | ext
| | | | | | | | warn |
--------------------------------------------------------------------------
KEY:
ext = The external net type is used
int = The internal net type is used
warn = A warning is issued
----------------------------------------------------------------------------
----------------------------------------------------------------------------
19.2 `default_nettype
In Syntax 19-1, CHANGE
trior|trireg|none
TO
trior|trireg|uwire|none
----------------------------------------------------------------------------
18.2.3.8 $var
AFTER THE NUMBERED LIST, ADD THE FOLLOWING PARAGRAPH:
In the $var section, a net of net type uwire shall have a variable type
of wire.
----------------------------------------------------------------------------
Annex G: vpi_user.h
AFTER:
#define vpiNone 12 /* no default net type (1364-2000) */
ADD:
#define vpiUwire 13 /* unresolved wire net (1364-2005) */
----------------------------------------------------------------------------
Annex B
ADD "uwire" to list of keywords.
<\pre>
|
| Unformatted |
----web-attachment---- wone.txt X-Authentication-Warning: isvw3.cadence.com: iscan owned process doing -bs Date: Thu, 28 Oct 2004 21:53:44 -0400 (EDT) From: Kathy McKinley <mckinley@cadence.com> To: btf@boyd.com Subject: Proposal for a 'wone' net type X-Received: By mailgate.Cadence.COM as SAA28702 at Thu Oct 28 18:54:02 2004 X-pstn-levels: (S:99.90000/99.90000 R:95.9108 P:95.9108 M:94.8624 C:98.9754 ) Hello, Here is the aforementioned proposal for introducing a new net type to enforce single-driver net semantics. Kathy ------------------------------------ ENFORCING SINGLE-DRIVER DESIGN RULES ------------------------------------ SystemVerilog allows variables to be driven by a single continuous assignment, like nets. This includes connecting variables to the "sink" side of a port (an input port in a module declaration, or an output port of a module instantiation). Unlike nets, they are not allowed to have multiple drivers, because their behavior would not resemble real hardware if they did. Some design styles restrict the use of multiple-driver nets. It has been suggested that if variables are used for connections, their limitations will have the side effect of acting as a design rule check. This is only true if a hardware net is represented with a variable everywhere in the hierarchy. If some part of the hierarchy (perhaps legacy code or some third-party IP) uses a net, then multiple drivers connected to that portion of the net will not be caught. For example, // New design in SystemVerilog module top; logic mout; ... mux m1(sel, in0, in1, mout); endmodule // Legacy Verilog code module mux (sel, in0, in1, mout); input sel, in0, in1; output mout; bufif0 b0(mout, sel, in0); bufif1 b1(mout, sel, in1); endmodule Inside module mux, mout has two drivers. This is legal because it is implicitly a wire. However, the logic variable mout in module top only has one driver: the implicit continuous assignment from the output port of m1. This is legal also. In the actual hardware, the wire and the variable will become the same net, which has two drivers. The limitation on variables has not enforced the design rule. This is not surprising, since it was not designed for that purpose. A new net type for enforcing single driver semantics for a net was proposed to the IEEE 1364 working group. The new net type, wone, explicitly indicates a desire for a net with only one driver. For example, the top-level module can be rewritten as: // New design in NC-Verilog module top; wone logic mout; ... mux m1(sel, in0, in1, mout); endmodule Because of port collapsing, the mout nets inside and outside module m1 will be collapsed into a single wone net. The presence of multiple drivers on that net will be detected and produce an error. A wone net type could complement the variable continuous assignment rules by providing single driver checking for nets. ------- DETAILS ------- Verilog net types, such as wire and trireg, determine how the value of a net is computed from its drivers. By extending the set of net types to include a single-driver net type, wone, we allow a user to specify that a single-driver design rule should be enforced. A wone net is very similar to a wire net. It differs in the following two ways: 1) It is an error for a wone net to have more than one driver 2) An implementation must either collapse a port connection to a wone net, or it must warn that it is not collapsing. When collapsing a wone port connection, the net type of the simulated net is resolved as follows: NET TYPE 1 NET TYPE 2 RESOLUTION WARNING wone wone wone No wone wire/tri wone No wone wand/triand wone Yes wone wor/trior wone Yes wone trireg wone Yes wone tri0 wone Yes wone tri1 wone Yes wone supply0 supply0 No wone supply1 supply1 No When the net type coercion results in a different behavior (such as when a trireg and a wone are connected, resulting in a wone), a warning must be issued. The `default_nettype compiler directive can be used to make the wone net type the default for implicit nets. |
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