| Add Proposal | Add Analysis | Edit Class, Environment, or Release |
| Number | 626
|
| Category | errata
|
| Synopsis | "time step" is not defined
|
| State | open
|
| Class | errata-discuss
|
| Arrival-Date | Sep 26 2004
|
| Originator | Shalom Bresticker <Shalom.Bresticker@freescale.com>
|
| Release | 2001b
|
| Description |
The term "time step" is not defined. It is first used in 5.3, second para. before the end. It is liable to be misinterpreted as something similar to "simulation cycle". There can be more than one simulation cycle during a single time point, as I understand it. The intended meaning of "time step" appears to be all the processing performed during a single simulation time point, which can be more than one simulation cycle. -- Shalom Bresticker Shalom.Bresticker @freescale.com Design & Verification Methodology Tel: +972 9 9522268 Freescale Semiconductor Israel, Ltd. Fax: +972 9 9522890 POB 2208, Herzlia 46120, ISRAEL Cell: +972 50 5441478 [ ]Freescale Internal Use Only [ ]Freescale Confidential Proprietary |
| Fix |
Unknown |
| Unformatted |
|
Hosted by Boyd Technology