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| Number | 597
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| Notify-List |
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| Category | errata
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| Synopsis | whitespace/comments within compiler directive
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| State | open
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| Class | errata-discuss
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| Arrival-Date | Jul 19 2004
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| Originator | Eric Mahurin
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| Description |
In general, I think there needs to be clarification of where and what kind of whitespace and comments can/should appear for compiler directives. I think whitespace and comments should be explicitly addressed for compiler directives because compiler directives are handled before parsing occurs and likely while lexing occurs (identifying identifiers, numbers, whitespace, and comments). The C preprocessor which is quite similar also has restrictions in this area and it would be good to give the same level of clarification. Here are the positions that I think need clarification about whitespace/comments: - Preceding a compiler directives on a line (excluding macro calls). Ex: assign a = `ifdef XYZ b `endif - Following a compiler directives command (excluding macro calls and `define - already specified). Ex: `else assign a=b; - Between the backtick and the directive keyword. Ex: `/**/define MAC - Between the directive keyword and/or its arguments. Ex: `line/**/1/**/"test.v" 1 - Between the `define and macro call macro identifier and "(" starting the macro argument list. Ex: `define MAC /**/ (a) a*a - Within the `define and macro call macro argument list. Ex: `define MAC( a /* , b ) */ , c ) - Multi-line comments within `define macro text. Ex: `define MAC(a,b) c /* (newline) */ * d |
| Fix |
Unknown |
| Audit-Trail |
From: Shalom.Bresticker@freescale.com To: eric_mahurin@yahoo.com Cc: etf-bugs@boyd.com Subject: Re: errata/597: whitespace/comments within compiler directive Date: Tue, 20 Jul 2004 16:27:48 +0300 (IDT) Eric, Your comments are welcome. However, before submitting a new erratum, please check whether it is already covered by an existing one. (In this case, #90.) Please introduce yourself to the group. Sincerely, Shalom Bresticker -- Shalom Bresticker Shalom.Bresticker @freescale.com Design & Reuse Methodology Tel: +972 9 9522268 Freescale Semiconductor Israel, Ltd. Fax: +972 9 9522890 POB 2208, Herzlia 46120, ISRAEL Cell: +972 50 5441478 From: Stefen Boyd <stefen@boyd.com> To: etf-bugs@boyd.com Cc: Subject: Re: errata/597: whitespace/comments within compiler directive Date: Mon, 26 Jul 2004 08:15:35 -0700 >Date: Tue, 20 Jul 2004 09:10:53 -0700 >From: mail <mail@boyd.com> >Subject: Failed bug submission from Eric Mahurin <eric_mahurin@yahoo.com>, >eric_mahurin@yahoo > > >From eric_mahurin@yahoo.com Tue Jul 20 09:10:52 2004 >Received: from web41111.mail.yahoo.com (web41111.mail.yahoo.com >[66.218.93.27]) > by wa.boyd.com (8.12.8/8.12.8) with SMTP id i6KGApKk011624 > for <etf-bugs@boyd.com>; Tue, 20 Jul 2004 09:10:51 -0700 >Message-ID: <20040720161430.52421.qmail@web41111.mail.yahoo.com> >Received: from [66.90.167.158] by web41111.mail.yahoo.com via HTTP; Tue, >20 Jul 2004 09:14:30 PDT >Date: Tue, 20 Jul 2004 09:14:30 -0700 (PDT) >From: Eric Mahurin <eric_mahurin@yahoo.com> >Subject: Re: errata/597: whitespace/comments within compiler directive >To: Shalom.Bresticker@freescale.com >Cc: etf-bugs@boyd.com >In-Reply-To: <Pine.GSO.4.10.10407201626190.15991-100000@eagle> >MIME-Version: 1.0 >Content-Type: text/plain; charset=us-ascii > >Hello everybody, > >Sorry I didn't mention #90 and also #330. I thought a > general clarification of whitespace/comments with >compiler directives was necessary. Both of these only >covered a portion what I thought was missing. > >Here is a little about me... My name is Eric Mahurin. > For the bulk of my career, I was a microprocessor >designer at AMD (K7, K8, and the next one). At AMD, >my areas of expertise include the following: > >- block/cell timing/power/noise characterization >(wrote tool used all throughout AMD). >- arithmetic design (designed integer execute cycle >for K7 and also designed cells for arithmetic) >- layout and route (wrote SPF route estimator and >later wrote cell layout generator) >- formal verification (methodology for handling >custom/dynamic/memory circuits) >- DFT/ATPG (involved in architecture, circuits, and >modeling) >- general cell (especially custom) modeling for >cooperation with all tools - static timing, >simulation, formal verification, ATPG, place&route, >etc. >- circuit design and layout - flip-flops, reg-files >(including all components), and arithmetic related >cells > >I left AMD last year and am now independent. My >primary client is Arithmatica where I've resumed >arithmetic design and significantly enhanced their >core technology. > >But, I'm also looking to start something else on my >own by leveraging my broad background. I am starting >with a verilog parser and am based it on the >verilog-2005 spec I found here. I thought it would be >a good idea to get involved. > >Eric > >--- Shalom.Bresticker@freescale.com wrote: > > Eric, > > > > Your comments are welcome. > > > > However, before submitting a new erratum, please > > check whether it is > > already covered by an existing one. (In this case, > > #90.) > > > > Please introduce yourself to the group. > > > > Sincerely, > > Shalom Bresticker > > > > -- > > Shalom Bresticker > > Shalom.Bresticker @freescale.com > > Design & Reuse Methodology > > Tel: +972 9 9522268 > > Freescale Semiconductor Israel, Ltd. > > Fax: +972 9 9522890 > > POB 2208, Herzlia 46120, ISRAEL > > Cell: +972 50 5441478 > > > > > > > > > > >__________________________________ >Do you Yahoo!? >Vote for the stars of Yahoo!'s next ad campaign! >http://advision.webevents.yahoo.com/yahoo/votelifeengine/ |
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