| Number | 461
|
| Category | enhancement
|
| Synopsis | Proposal: Eliminate IEEE Enhancements Submission Deadline
|
| State | closed
|
| Class | mistaken
|
| Arrival-Date | Sep 03 2003
|
| Originator | "Clifford E. Cummings" <cliffc@sunburst-design.com>
|
| Release |
|
| Environment |
|
| Description |
Hi, All - I have been very busy this Summer and unable to attend a number of the IEEE Verilog meetings. I guess I have missed some good fireworks! It has been brought to my attention that the IEEE Verilog committee has given a donations deadline of end-of-August for Verilog-2005 donations. I understand the reasoning for the timeline: · We want Verilog-2005 to be the next IEEE Verilog Standard. · It takes 1 year to ballot, respond and RevCom IEEE formalize the Verilog Standard (balloting must start Summer 2004). · It takes time to review donations, make proposals, etc (we need donations now - next Summer is too late). Ideally we would have the SystemVerilog donation now to have ample time to debate and add approved portions to the IEEE Verilog Standard. Personally, I would like to see most of it added unchanged and other portions I would like debated by actual users. I have done a quick search of the minutes (translation - I may have missed what I was searching for) and could not find where the IEEE committee voted to cut off donations by the end of August. Further, I am opposed to cutting off donations (even though I understand the above timeline). I do not believe a donations deadline is appropriate. I believe donations can be made right up to the time we go to ballot, but we may not have time to consider donations that arrive too late. At some point late next Spring we will have to stop enhancement work, clean up the documentation in preparation for going to ballot and push unfinished work into Verilog-2007 or whatever the next version is, but I don't think it is a good idea to draw a line in the sand and say that we will not consider SystemVerilog enhancements. I helped proposed a number of the SystemVerilog enhancements, and hope that a donation is made before too long so that I can champion those enhancements in the IEEE Verilog committee. PROPOSAL: I propose that we eliminate donation deadlines with the understanding that late-arriving donations may naturally not make it into the Verilog-2005 Standard. Does anyone second? I am not trying to stir any rules or legalities hornets nests, I just don't think it is wise to issue a donations deadline, especially with all of the other politics that are in play right now. I have been asked to comment for EE Times and I intend to do so. I will make it clear that my comments are my own opinion and I will try to smooth some of the rifts that have been suggested by the questions that have been sent my way. Regards - Cliff ---------------------------------------------------- Cliff Cummings - Sunburst Design, Inc. 14314 SW Allen Blvd., PMB 501, Beaverton, OR 97005 Phone: 503-641-8446 / FAX: 503-641-8486 cliffc@sunburst-design.com / www.sunburst-design.com Expert Verilog, Synthesis and Verification Training |
| Fix |
|
| Audit-Trail |
From: Shalom.Bresticker@motorola.com To: "Clifford E. Cummings" <cliffc@sunburst-design.com> Cc: etf-bugs@boyd.com Subject: Re: enhancement/461: Proposal: Eliminate IEEE Enhancements Submission Deadline Date: Thu, 4 Sep 2003 08:34:35 +0300 (IDT) Cliff, Without prejudice to your actual proposal (I have not even read it in full yet), I don't think it belongs in the database, so I suggest that Stefen Boyd delete it and that you bring up the issue for discussion in Monday's BTF meeting (1030 Pacific time). -- Shalom Bresticker Shalom.Bresticker@motorola.com Design & Reuse Methodology Tel: +972 9 9522268 Motorola Semiconductor Israel, Ltd. Fax: +972 9 9522890 POB 2208, Herzlia 46120, ISRAEL Cell: +972 50 441478 |
| Unformatted |
|
Hosted by Boyd Technology