| Number | 441
|
| Category | errata
|
| Synopsis | 3.2.2, 4.1.6: Nets also have signedness
|
| State | lrmdraft
|
| Class | errata-simple
|
| Arrival-Date | Aug 25 2003
|
| Originator | Shalom Bresticker <Shalom.Bresticker@motorola.com>
|
| Release | 2001b: 3.2.2, 4.1.6
|
| Environment |
|
| Description |
Both the CAUTION box at the end of Section 3.2.2 and section 4.1.6 have sentences which relate to signedness of reg variables while ignoring nets. Specifically, the CAUTION box says, "Variables can be assigned negative values, but only signed regs, integer, real, and realtime variables shall retain the significance of the sign. The unsigned reg and time variables shall treat the value assigned to them as an unsigned value". It should be rewritten as, "Nets and variables can be assigned negative values, but only integer, real, realtime and signed reg variables and signed nets shall retain the significance of the sign. Time and unsigned reg variables and unsigned nets shall treat the value assigned to them as an unsigned value". Similarly, 4.1.6 begins, "A reg data type shall be treated as an unsigned value unless explicitly declared to be signed. " It should be "Net and reg data types shall be treated as unsigned values unless explicitly declared to be signed. " -- Shalom Bresticker Shalom.Bresticker@motorola.com Design & Reuse Methodology Tel: +972 9 9522268 Motorola Semiconductor Israel, Ltd. Fax: +972 9 9522890 POB 2208, Herzlia 46120, ISRAEL Cell: +972 50 441478 |
| Fix |
In the CAUTION box of 3.2.2 CHANGE "Variables can be assigned negative values, but only signed regs, integer, real, and realtime variables shall retain the significance of the sign. The unsigned reg and time variables shall treat the value assigned to them as an unsigned value. Refer to 4.1.6 for a description of how signed and unsigned variables are treated by certain Verilog operators." TO "Nets and variables can be assigned negative values, but only integer, real, realtime and signed reg variables and signed nets shall retain the significance of the sign. Time and unsigned reg variables and unsigned nets shall treat the value assigned to them as an unsigned value. Refer to 4.1.6 for a description of how signed and unsigned nets and variables are treated by certain Verilog operators." and in 4.1.6 CHANGE "A reg data type shall be treated as an unsigned value unless explicitly declared to be signed. An integer variable shall be treated as signed. Signed values shall use a 2's complement representation." TO "A value assigned to a reg variable or net shall be treated as an unsigned value unless the reg variable or net has been explicitly declared to be signed. A value assigned to an integer, real or realtime variable shall be treated as signed. A value assigned to a time variable shall be treated as unsigned. Signed values, except for those assigned to real and realtime variables, shall use a 2's complement representation. Values assigned to real and realtime variables shall use a floating-point representation." |
| Audit-Trail |
From: Shalom Bresticker <Shalom.Bresticker@motorola.com> To: Brad.Pierce@synopsys.com Cc: etf-bugs@boyd.com Subject: Re: errata/441: PROPOSAL - 3.2.2, 4.1.6: Nets also have signedness Date: Wed, 01 Oct 2003 16:49:57 +0300 Looks good, but now what about parameters? Shalom Brad.Pierce@synopsys.com wrote: > In the CAUTION box of 3.2.2 > > CHANGE > > "Variables can be assigned negative values, > but only signed regs, integer, real, and > realtime variables shall retain the significance > of the sign. The unsigned reg and time variables > shall treat the value assigned to them as an > unsigned value. Refer to 4.1.6 for a description > of how signed and unsigned variables are treated > by certain Verilog operators." > > TO > > "Nets and variables can be assigned negative values, > but only integer, real, realtime and signed reg > variables and signed nets shall retain the > significance of the sign. Time and unsigned > reg variables and unsigned nets shall treat the > value assigned to them as an unsigned value. > Refer to 4.1.6 for a description of how signed > and unsigned nets and variables are treated by > certain Verilog operators." > > and in 4.1.6 > > CHANGE > > "A reg data type shall be treated as an unsigned > value unless explicitly declared to be signed. > An integer variable shall be treated as signed. > Signed values shall use a 2's complement > representation." > > TO > > "A value assigned to a reg variable or net > shall be treated as an unsigned value unless > the reg variable or net has been explicitly > declared to be signed. A value assigned to an > integer, real or realtime variable shall be treated > as signed. A value assigned to a time variable > shall be treated as unsigned. Signed values, > except for those assigned to real and realtime > variables, shall use a 2's complement representation. > Values assigned to real and realtime variables > shall use a floating-point representation." > > http://boydtechinc.com/cgi-bin/issueproposal.pl?cmd=view&pr=441 -- Shalom Bresticker Shalom.Bresticker@motorola.com Design & Reuse Methodology Tel: +972 9 9522268 Motorola Semiconductor Israel, Ltd. Fax: +972 9 9522890 POB 2208, Herzlia 46120, ISRAEL Cell: +972 50 441478 |
| Unformatted |
|
Hosted by Boyd Technology