ISSUE 430

Edit Proposal  Edit Class, Environment, or Release
Number 430
Category enhancement
Synopsis Add `pragma compiler directive
State proposal
Class enhancement
Arrival-DateAug 22 2003
Originator Jay Lawrence - Cadence Design Systems
Release 2005
Environment
Description

The following enhancment proposes a new compiler directive intended to allow for including lexically scoped information in a description. This enhancment is motivated by the desire to eliminate the use of comments as a way of embedding content in a description.

Comments in any language are intended to allow the embedding of arbitrary text in a source file. They are intended to make the code more readable and document the functionality and are commonly used for content like copyright notices and revision control information. Over the years however, a form of proprietary language extension has been widely used in the Verilog community by embedding special tokens within comments.

Examples of this include:
// synopsys full_case
// 0-in known_drive
// Sugar assert

This mechanism, first proliferated by synthesis specific directives, has become widely adopted in the industry at this point. It is attractive because the data is inside a comment and tools which do not understand the specific keyword sequence following the comment character just interpret the line as a comment and ignore the content. Its use however points out the need for being able to associate vendor, tool, or methodology specific data with a design in two ways, lexically and syntactically.

A lexical association is one that is has meaning based solely on where it occurs in the source text, not where it occurs relative to the Verilog grammar. The best example of this are the translate_off and translate_on directives commonly used to indicate that a region of a file is not intended for synthesis. These directives can occur anywhere in a source file and have no specified relationship to a given grammatical construct.

To handle the case of lexical association, I proposes a new `pragma compiler directive. This proposal is included in this enhancement request.

A syntactic association is one that is associated syntactically with the design. For instance a full_case directive occurs in specific locations near or in a case statement and applies to that specific statement. Similarly a one_hot directive applies to the registers declared syntactically in the declaration to which the one_hot directive is applied.

To handle the case of syntactic association, a second enhancement will be added that proposes system attributes as a language standard mechanism.
Fix
The following is proposed as the content of clause 19.10 `pragma.


19.10 `pragma

The pragma directive is provided to allow user, vendor, or language-standard defined information to be placed lexically within a description. The syntax for the pragma directive is:

pragma_directive ::=
`pragma <pragma_name> <pragma_arguments>

pragma_name ::=
system_identifier
| identifier

system_identifier ::= $identifier

The name following the pragma keyword is any system identifier or identifier. The use of system identifiers is reserved for pragma names that are defined by the language standard. This provision is included so that the language can be safely extended in the future without conflict with user or vendor defined pragma names.

The pragma name serves only to identify the pragma to tools that understand that particular pragma. Implementations may ignore pragmas that they do not recognize, do not choose to implement, or that are not appropriate for a particular tool.

The pragma arguments are additional information that is specific to a given pragma definition. The language does not specify the format of this information. It shall extend until the end of the current line.

19.10.1 $translate_off/$translate_on

The $translate_off/$translate_on pragma are intended to bracket code that is included in an RTL description but is not appropriate for synthesis or inclusion in an actual physical implementation of a description.

$translate_off indicates the beginning of a region to be excluded.

$translate_on indicates the end of a region to be excluded.

Example:

always @(posedge clk)
begin
`pragma $translate_off
if (debug_flag) $display("Hello, world");
`pragma $translate_on
if (!reset)
q <= d;
end


Audit-Trail

From: Shalom.Bresticker@motorola.com
To: lawrence@cadence.com
Cc: etf-bugs@boyd.com
Subject: Re: enhancement/430: PROPOSAL - Add `pragma compiler directive
Date: Sat, 23 Aug 2003 23:37:46 +0300 (IDT)

Why should $translate_off be specifically for synthesis?
Why not a more meaningful name?
Why not `ifdef?

> The $translate_off/$translate_on pragma are intended to bracket code that is included in an RTL description but is not appropriate for synthesis or inclusion in an actual physical implementation of a description.


From: "Jay Lawrence" <lawrence@cadence.com>
To: <Shalom.Bresticker@motorola.com>, <etf-bugs@boyd.com>
Cc:
Subject: RE: enhancement/430: PROPOSAL - Add `pragma compiler directive
Date: Sun, 24 Aug 2003 21:03:26 -0400

`ifdef is subtly different. With a `ifdef the code is treated by the
pre-processor and never even seen by the lexer as if it didn't exist.
With `translate_on/off, it can be treated as if it exists and stored
specially so that a single compile can be used for both simulation and
synthesis.

A better name would be appropriate if the committee so decided.
Transalate_on/off were suggested because of the existing wied-spread
use.

Jay




===================================
Jay Lawrence
Senior Architect
Functional Verification
Cadence Design Systems, Inc.
(978) 262-6294
lawrence@cadence.com
===================================

> -----Original Message-----
> From: Shalom.Bresticker@motorola.com
> [mailto:Shalom.Bresticker@motorola.com]
> Sent: Saturday, August 23, 2003 4:50 PM
> To: etf-bugs@boyd.com
> Subject: Re: enhancement/430: PROPOSAL - Add `pragma compiler
> directive
>
>
> Precedence: bulk
>
> The following reply was made to PR enhancement/430; it has
> been noted by GNATS.
>
> From: Shalom.Bresticker@motorola.com
> To: lawrence@cadence.com
> Cc: etf-bugs@boyd.com
> Subject: Re: enhancement/430: PROPOSAL - Add `pragma compiler
> directive
> Date: Sat, 23 Aug 2003 23:37:46 +0300 (IDT)
>
> Why should $translate_off be specifically for synthesis?
> Why not a more meaningful name?
> Why not `ifdef?
>
> > The $translate_off/$translate_on pragma are intended to
> bracket code that is included in an RTL description but is
> not appropriate for synthesis or inclusion in an actual
> physical implementation of a description.
>
>

From: "Jay Lawrence" <lawrence@cadence.com>
To: "Jayaram Bhasker" <JBhasker@eSilicon.com>, <etf-bugs@boyd.com>
Cc:
Subject: RE: enhancement/430: PROPOSAL - Add `pragma compiler directive
Date: Tue, 26 Aug 2003 08:58:01 -0400

There are 2 issues here:

1) Should we have a `pragma directive so that users, vendors, and the
language definition can define new lexically associated information
without using // pragma.

2) Is $translate_on/off a good way to do this.

I strongly believe the answer to #1 is yes because for the last 5 years
vendors have been embedding content in comments because this facility
did not exist. Therefore I believe the base pragma capability is a no
brainer.

As for #2, we can choose or not to begin to define a set of
language-defined pragmas such as translate_on/translate_off. As I said
in my not to Shalom on this topic, `ifdef/`ifndef are defined to be
preprocessor directives where the content between them does not even
have to be syntactically legal

`ifndef ALLOW_GARBAGE

Anthing can be written here

`endif

If you use these for synthesis then it is required to recompile the
design between synthesis (or formal verification or some forms of lint
checks) and simulation.

With `pragma it is possible to avoid the recompilation. This is
especially important in the case of IP where you may want to deliver one
model that can be used for both simulation and synthesis/formal.

Would it be useful for me to break this into 2 enhancements? One for
`pragma and another for $translate_on/off. I'ld be glad to do so.

Jay



===================================
Jay Lawrence
Senior Architect
Functional Verification
Cadence Design Systems, Inc.
(978) 262-6294
lawrence@cadence.com
===================================

> -----Original Message-----
> From: Jayaram Bhasker [mailto:JBhasker@eSilicon.com]
> Sent: Tuesday, August 26, 2003 8:48 AM
> To: Jay Lawrence; etf-bugs@boyd.com
> Subject: RE: enhancement/430: PROPOSAL - Add `pragma compiler
> directive
>
>
> The 1364.1 IEEE standard already defines what is to be used
> for synthesis.
> It is a special macro SYNTHESIS which can be used in contexts such as:
>
> 'ifndef SYNTHESIS
> . . .
>
> Defined under Clause 6.2, IEEE Std 1364.1-2002.
>
> - bhasker
>
> ------
> J. Bhasker, eSilicon Corp
> 1605 N. Cedar Crest Blvd, Ste 615, Allentown, PA 18104
> jbhasker@esilicon.com, 610.439.6831, 610.770.9634(fax)
>
>
>
> -----Original Message-----
> From: Jay Lawrence [mailto:lawrence@cadence.com]
> Sent: Sunday, August 24, 2003 9:40 PM
> To: etf-bugs@boyd.com
> Subject: RE: enhancement/430: PROPOSAL - Add `pragma compiler
> directive
>
>
> Precedence: bulk
>
> The following reply was made to PR enhancement/430; it has
> been noted by GNATS.
>
> From: "Jay Lawrence" <lawrence@cadence.com>
> To: <Shalom.Bresticker@motorola.com>, <etf-bugs@boyd.com>
> Cc:
> Subject: RE: enhancement/430: PROPOSAL - Add `pragma compiler
> directive
> Date: Sun, 24 Aug 2003 21:03:26 -0400
>
> `ifdef is subtly different. With a `ifdef the code is treated by the
> pre-processor and never even seen by the lexer as if it didn't exist.
> With `translate_on/off, it can be treated as if it exists and stored
> specially so that a single compile can be used for both
> simulation and
> synthesis.
>
> A better name would be appropriate if the committee so decided.
> Transalate_on/off were suggested because of the existing wied-spread
> use.
>
> Jay
>
>
>
>
> ===================================
> Jay Lawrence
> Senior Architect
> Functional Verification
> Cadence Design Systems, Inc.
> (978) 262-6294
> lawrence@cadence.com
> ===================================
>
> > -----Original Message-----
> > From: Shalom.Bresticker@motorola.com
> > [mailto:Shalom.Bresticker@motorola.com]
> > Sent: Saturday, August 23, 2003 4:50 PM
> > To: etf-bugs@boyd.com
> > Subject: Re: enhancement/430: PROPOSAL - Add `pragma compiler
> > directive
> >
> >
> > Precedence: bulk
> >
> > The following reply was made to PR enhancement/430; it has
> > been noted by GNATS.
> >
> > From: Shalom.Bresticker@motorola.com
> > To: lawrence@cadence.com
> > Cc: etf-bugs@boyd.com
> > Subject: Re: enhancement/430: PROPOSAL - Add `pragma compiler
> > directive
> > Date: Sat, 23 Aug 2003 23:37:46 +0300 (IDT)
> >
> > Why should $translate_off be specifically for synthesis?
> > Why not a more meaningful name?
> > Why not `ifdef?
> >
> > > The $translate_off/$translate_on pragma are intended to
> > bracket code that is included in an RTL description but is
> > not appropriate for synthesis or inclusion in an actual
> > physical implementation of a description.
> >
> >
>

From: Shalom Bresticker <Shalom.Bresticker@motorola.com>
To: Jay Lawrence <lawrence@cadence.com>
Cc: etf-bugs@boyd.com
Subject: Re: enhancement/430: PROPOSAL - Add `pragma compiler directive
Date: Tue, 26 Aug 2003 16:29:50 +0300

Two points:

- There is no reason that translate_off/on should be specific to synthesis only.

- Re "the content between `ifdef/`ifndef does not even have to be syntactically
legal":

This is only partly true: The LRM states (following the Verilog-XL User Guide)
that,

"Any group of lines that the compiler ignores still has to follow the Verilog HDL
lexical conventions for white space, comments, numbers, strings, identifiers,
keywords, and operators."

So for example, you could not write

`ifdef cucu
1A
`endif

because "1A" is not a legal token.

Shalom


--
Shalom Bresticker Shalom.Bresticker@motorola.com
Design & Reuse Methodology Tel: +972 9 9522268
Motorola Semiconductor Israel, Ltd. Fax: +972 9 9522890
POB 2208, Herzlia 46120, ISRAEL Cell: +972 50 441478




From: "Jay Lawrence" <lawrence@cadence.com>
To: "Shalom Bresticker" <Shalom.Bresticker@motorola.com>
Cc: <etf-bugs@boyd.com>
Subject: RE: enhancement/430: PROPOSAL - Add `pragma compiler directive
Date: Tue, 26 Aug 2003 09:39:28 -0400

Thanks for the correction on the token part Shalom, I learned something
today!

Another point in the original proposal is the idea of defining a new set
of identifiers, either $translate_on/$translate_off or
_translate_on/_translate_off so that they will never conflict with a
legal user identifier.

If 1364.1 has used SYNTHESIS, then it could possibly conflict with a
user-defined macro.

Adopting a new set of "system_identifiers" as suggested here and in the
enhancment for attributes will allow the language to define pragmas and
attributes that will never conflict with a user name (except in the case
of escaped names and I can live with that).

Jay




===================================
Jay Lawrence
Senior Architect
Functional Verification
Cadence Design Systems, Inc.
(978) 262-6294
lawrence@cadence.com
===================================

> -----Original Message-----
> From: Shalom Bresticker [mailto:Shalom.Bresticker@motorola.com]
> Sent: Tuesday, August 26, 2003 9:30 AM
> To: Jay Lawrence
> Cc: etf-bugs@boyd.com
> Subject: Re: enhancement/430: PROPOSAL - Add `pragma compiler
> directive
>
>
> Two points:
>
> - There is no reason that translate_off/on should be specific
> to synthesis only.
>
> - Re "the content between `ifdef/`ifndef does not even have
> to be syntactically
> legal":
>
> This is only partly true: The LRM states (following the
> Verilog-XL User Guide)
> that,
>
> "Any group of lines that the compiler ignores still has to
> follow the Verilog HDL
> lexical conventions for white space, comments, numbers,
> strings, identifiers,
> keywords, and operators."
>
> So for example, you could not write
>
> `ifdef cucu
> 1A
> `endif
>
> because "1A" is not a legal token.
>
> Shalom
>
>
> --
> Shalom Bresticker
> Shalom.Bresticker@motorola.com
> Design & Reuse Methodology Tel:
> +972 9 9522268
> Motorola Semiconductor Israel, Ltd. Fax:
> +972 9 9522890
> POB 2208, Herzlia 46120, ISRAEL Cell:
> +972 50 441478
>
>
>
>

From: Stefen Boyd <stefen@boyd.com>
To: etf-bugs@boyd.com
Cc:
Subject: RE: enhancement/430: PROPOSAL - Add `pragma compiler directive
Date: Tue, 26 Aug 2003 14:40:23 -0700

fwd:

>Subject: RE: enhancement/430: PROPOSAL - Add `pragma compiler directive
>Date: Tue, 26 Aug 2003 08:47:37 -0400
>From: "Jayaram Bhasker" <JBhasker@eSilicon.com>
>To: "Jay Lawrence" <lawrence@cadence.com>, <etf-bugs@boyd.com>
>
>The 1364.1 IEEE standard already defines what is to be used for synthesis.
>It is a special macro SYNTHESIS which can be used in contexts such as:
>
>'ifndef SYNTHESIS
>. . .
>
>Defined under Clause 6.2, IEEE Std 1364.1-2002.
>
>- bhasker
>
>------
>J. Bhasker, eSilicon Corp
>1605 N. Cedar Crest Blvd, Ste 615, Allentown, PA 18104
>jbhasker@esilicon.com, 610.439.6831, 610.770.9634(fax)
>
>
>
>-----Original Message-----
>From: Jay Lawrence [mailto:lawrence@cadence.com]
>Sent: Sunday, August 24, 2003 9:40 PM
>To: etf-bugs@boyd.com
>Subject: RE: enhancement/430: PROPOSAL - Add `pragma compiler directive
>
>
>Precedence: bulk
>
>The following reply was made to PR enhancement/430; it has been noted by
>GNATS.
>
>From: "Jay Lawrence" <lawrence@cadence.com>
>To: <Shalom.Bresticker@motorola.com>, <etf-bugs@boyd.com>
>Cc:
>Subject: RE: enhancement/430: PROPOSAL - Add `pragma compiler directive
>Date: Sun, 24 Aug 2003 21:03:26 -0400
>
> `ifdef is subtly different. With a `ifdef the code is treated by the
> pre-processor and never even seen by the lexer as if it didn't exist.
> With `translate_on/off, it can be treated as if it exists and stored
> specially so that a single compile can be used for both simulation and
> synthesis.
>
> A better name would be appropriate if the committee so decided.
> Transalate_on/off were suggested because of the existing wied-spread
> use.
>
> Jay
>
>
>
>
> ===================================
> Jay Lawrence
> Senior Architect
> Functional Verification
> Cadence Design Systems, Inc.
> (978) 262-6294
> lawrence@cadence.com
> ===================================
>
> > -----Original Message-----
> > From: Shalom.Bresticker@motorola.com
> > [mailto:Shalom.Bresticker@motorola.com]
> > Sent: Saturday, August 23, 2003 4:50 PM
> > To: etf-bugs@boyd.com
> > Subject: Re: enhancement/430: PROPOSAL - Add `pragma compiler
> > directive
> >
> >
> > Precedence: bulk
> >
> > The following reply was made to PR enhancement/430; it has
> > been noted by GNATS.
> >
> > From: Shalom.Bresticker@motorola.com
> > To: lawrence@cadence.com
> > Cc: etf-bugs@boyd.com
> > Subject: Re: enhancement/430: PROPOSAL - Add `pragma compiler
> > directive
> > Date: Sat, 23 Aug 2003 23:37:46 +0300 (IDT)
> >
> > Why should $translate_off be specifically for synthesis?
> > Why not a more meaningful name?
> > Why not `ifdef?
> >
> > > The $translate_off/$translate_on pragma are intended to
> > bracket code that is included in an RTL description but is
> > not appropriate for synthesis or inclusion in an actual
> > physical implementation of a description.
> >
> >


From: Steven Sharp <sharp@cadence.com>
To: etf-bugs@boyd.com, lawrence@cadence.com
Cc:
Subject: RE: enhancement/430: PROPOSAL - Add `pragma compiler directive
Date: Tue, 26 Aug 2003 23:05:51 -0400 (EDT)

> 1) Should we have a `pragma directive so that users, vendors, and the
> language definition can define new lexically associated information
> without using // pragma.
>
> 2) Is $translate_on/off a good way to do this.
>
> I strongly believe the answer to #1 is yes because for the last 5 years
> vendors have been embedding content in comments because this facility
> did not exist. Therefore I believe the base pragma capability is a no
> brainer.

But the majority of these can be handled with attributes attached to an
appropriate object. $translate_on/off is the only one I am aware of that
cannot be handled with an attribute. Are there any other examples of
pragmas that need to be handled lexically?


> If you use these for synthesis then it is required to recompile the
> design between synthesis (or formal verification or some forms of lint
> checks) and simulation.
>
> With `pragma it is possible to avoid the recompilation. This is
> especially important in the case of IP where you may want to deliver one
> model that can be used for both simulation and synthesis/formal.

Are there any existing tool sets that support both synthesis and simulation
with the same front end compiler?

Steven Sharp
sharp@cadence.com


From: Shalom Bresticker <Shalom.Bresticker@motorola.com>
To: Steven Sharp <sharp@cadence.com>
Cc: etf-bugs@boyd.com
Subject: Re: enhancement/430: PROPOSAL - Add `pragma compiler directive
Date: Wed, 27 Aug 2003 08:59:40 +0300

I would want an equivalence checker to be able to do that.


> Are there any existing tool sets that support both synthesis and simulation
> with the same front end compiler?

--
Shalom Bresticker Shalom.Bresticker@motorola.com
Design & Reuse Methodology Tel: +972 9 9522268
Motorola Semiconductor Israel, Ltd. Fax: +972 9 9522890
POB 2208, Herzlia 46120, ISRAEL Cell: +972 50 441478




From: Shalom Bresticker <Shalom.Bresticker@motorola.com>
To: lawrence@cadence.com
Cc: etf-bugs@boyd.com
Subject: Re: enhancement/430: PROPOSAL - Add `pragma compiler directive
Date: Wed, 27 Aug 2003 09:16:10 +0300

Assuming system_identifer to be syntactically the same as system_function_identifier and system_task_identifier, then it is not correct to write:

system_identifier ::= $identifier

Reasons:

- "identifier" can be escaped, whereas system_identifier should not allow escape backslash character after the $

- "identifier" must begin with a letter or underscore, whereas system_identifier allows a digit or $ to follow the first $.

--
Shalom Bresticker Shalom.Bresticker@motorola.com
Design & Reuse Methodology Tel: +972 9 9522268
Motorola Semiconductor Israel, Ltd. Fax: +972 9 9522890
POB 2208, Herzlia 46120, ISRAEL Cell: +972 50 441478




From: Stephen Williams <steve@icarus.com>
To: Steven Sharp <sharp@cadence.com>
Cc: etf-bugs@boyd.com
Subject: Re: enhancement/430: PROPOSAL - Add `pragma compiler directive
Date: Wed, 27 Aug 2003 08:42:32 -0700

Steven Sharp wrote:
> Precedence: bulk
>
> Are there any existing tool sets that support both synthesis and simulation
> with the same front end compiler?

Icarus Verilog does both, although the synthesis is not exactly
highly competitive. However, I use attributes to do the equivilent
of the translate on/off pragmas proposed here. The attributes work
fine as far as I'm concerned.
--
Steve Williams "The woods are lovely, dark and deep.
steve at icarus.com But I have promises to keep,
http://www.icarus.com and lines to code before I sleep,
http://www.picturel.com And lines to code before I sleep."


From: "Jay Lawrence" <lawrence@cadence.com>
To: "Stephen Williams" <steve@icarus.com>, <etf-bugs@boyd.com>
Cc:
Subject: RE: enhancement/430: PROPOSAL - Add `pragma compiler directive
Date: Thu, 28 Aug 2003 06:59:08 -0400

The issue is not just simulation/synthesis. It is any other tool that
wants to see the "hardware" view of a model. This could be running on
an emulator, a model checking tool, an equivalence checker, and anything
else that wants to see the cycle accurate view of a device.

Attributes are not sufficient. There are cases where a single construct
is not where the information is associated. Sometimes it is just and
expression (like an initial value on a port), sometimes it is a set of
statements (not just a single statement). We have see numerous
benchmarks with this kind of usage.

Please don't misunderstand, I also think attributes should be used in
the cases where it is a specific language feature like one_hot on a
register or full_case/parallel_case on a case statement, that is why I
proposed system attributes in a separate enhancment.

Lastly, translate_on/translate_off is only one example. Any other pragma
that a user, vendor or the language may want to define could also use
this mechanism.

jay



===================================
Jay Lawrence
Senior Architect
Functional Verification
Cadence Design Systems, Inc.
(978) 262-6294
lawrence@cadence.com
===================================

> -----Original Message-----
> From: Stephen Williams [mailto:steve@icarus.com]
> Sent: Wednesday, August 27, 2003 11:50 AM
> To: etf-bugs@boyd.com
> Subject: Re: enhancement/430: PROPOSAL - Add `pragma compiler
> directive
>
>
> Precedence: bulk
>
> The following reply was made to PR enhancement/430; it has
> been noted by GNATS.
>
> From: Stephen Williams <steve@icarus.com>
> To: Steven Sharp <sharp@cadence.com>
> Cc: etf-bugs@boyd.com
> Subject: Re: enhancement/430: PROPOSAL - Add `pragma compiler
> directive
> Date: Wed, 27 Aug 2003 08:42:32 -0700
>
> Steven Sharp wrote:
> > Precedence: bulk
> >
> > Are there any existing tool sets that support both
> synthesis and simulation
> > with the same front end compiler?
>
> Icarus Verilog does both, although the synthesis is not exactly
> highly competitive. However, I use attributes to do the equivilent
> of the translate on/off pragmas proposed here. The attributes work
> fine as far as I'm concerned.
> --
> Steve Williams "The woods are lovely, dark and deep.
> steve at icarus.com But I have promises to keep,
> http://www.icarus.com and lines to code before I sleep,
> http://www.picturel.com And lines to code before I sleep."
>
>
Unformatted



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