ISSUE 385

Add Proposal  Add Analysis  Edit Class, Environment, or Release
Number 385
Category enhancement
Synopsis interconnect net that resolves to type
State open
Class enhancement
Arrival-DateJul 09 2003
Originator sharp@cadence.com
Release 2001b
Environment

Description
This is a request from my Verilog-AMS contact.

All I have is the description in the synopsis above. With
what little I can tell from that, I may not approve of this
being added to Verilog. It sounds like something that calls
for deferring the determination of information about a net
until it is known what it is connected to. Verilog already
does too much deferring of things until elaboration, and it
causes inefficient compilation. Clearly we would need a
more detailed description. This is just a placeholder for
the request.
Fix

Audit-Trail
Unformatted

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