| Add Proposal | Add Analysis | Edit Class, Environment, or Release |
| Number | 383
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| Category | enhancement
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| Synopsis | add inherited connections
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| State | open
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| Class | enhancement
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| Arrival-Date | Jul 09 2003
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| Originator | sharp@cadence.com
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| Release | 2001b
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| Description |
This is a request from my Verilog-AMS contact. They would like Verilog to support "inherited connections", a feature of Verilog-AMS. I believe that they are currently using attributes to implement this, which is a complete misuse of attributes (since they are not supposed to have any effect on the language semantics). They would need to provide a different syntax/mechanism for this. I don't know the details about inherited connections, but I suspect that they cause a variety of implementation problems. I may oppose actually adding them to Verilog, but am just passing along the request and adding this as a placeholder for it. |
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| Audit-Trail |
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| Unformatted |
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