ISSUE 381

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Number 381
Category enhancement
Synopsis table model system task
State analyzed
Class enhancement
Arrival-DateJul 09 2003
Originator sharp@cadence.com
Release 2001b
Environment
Description
This is an item that was requested by my Verilog-AMS
contact.

It involves a system task that accepts a table and
input value and does a table lookup, possibly with
interpolation. This is apparently from the Verilog-AMS
LRM, after version 2.0.

We would need to get more detail on this. If it would
be useful to Verilog users, I don't see any problems
with adding such a system task.
Fix

Audit-Trail

Analyzed by cranston@cadence.com on Tue Aug 5 06:09:11 2003
More info on the reasoning behind this one. Some analog/mixed-signal users may choose to do some or all of their modeling in Verilog performance reasons (using real variables, etc.). Having this system task available in initial blocks would allow these users to do this.



From: Steven Sharp <sharp@cadence.com>
To: etf-bugs@boyd.com, cranston@cadence.com
Cc:
Subject: Re: enhancement/381: ANALYZED - table model system task
Date: Tue, 5 Aug 2003 15:21:51 -0400 (EDT)

The exact algorithm for the lookup would have to be specified, particularly
for any kind of interpolation.

Steven Sharp
sharp@cadence.com

Unformatted



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