ISSUE 338

Number 338
Category errata
Synopsis Syntax 14-4, A.7.4: syntax of edge sensitive module path descriptions
State lrmdraft
Class errata-simple
Arrival-DateApr 29 2003
Originator Dennis Marsa <drm@xilinx.com>
Release 2001b: Syntax 14-4, A.7.4
Environment
Description
In 1364-1995, the syntax for edge sensitive module path
descriptions is described by the following BNF rules
in A.7, and in syntax box 13-5.

parallel_edge_sensitive_path_description ::=
"(" [ edge_identifier ] specify_input_terminal_descriptor "=>"
specify_output_terminal_descriptor [ polarity_operator ] ":" data_source_expression ")"
")"

full_edge_sensitive_path_description ::=
"(" [ edge_identifier ] list_of_path_inputs "*>"
list_of_path_outputs [ polarity_operator ] ":" data_source_expression ")" ")"

In 1364-2001, the syntax for edge sensitive module path
descriptions was changed to the following (in A.7.4, and
in syntax box 14-4):

parallel_edge_sensitive_path_description ::=
"(" [ edge_identifier ] specify_input_terminal_descriptor "=>"
specify_output_terminal_descriptor [ polarity_operator ] ":" data_source_expression ")"

full_edge_sensitive_path_description ::=
"(" [ edge_identifier ] list_of_path_inputs "*>"
list_of_path_outputs [ polarity_operator ] ":" data_source_expression ")"

The difference is that the closing ")" was removed in each rule. In the 1364-1995
syntax there is one opening "(" and two closing ")", so they are not balanced. In
1364-2001 they are now balanced.


Does 1364-2001 indicate the proper syntax?


Perhaps not. Verilog-XL, NC-Verilog, and MTI all seem to want to parse the following
third syntax for edge sensitive module path descriptions:

parallel_edge_sensitive_path_description ::=
"(" [ edge_identifier ] specify_input_terminal_descriptor "=>"
"(" specify_output_terminal_descriptor [ polarity_operator ] ":" data_source_expression
")" ")"

full_edge_sensitive_path_description ::=
"(" [ edge_identifier ] list_of_path_inputs "*>"
"(" list_of_path_outputs [ polarity_operator ] ":" data_source_expression ")" ")"

The difference between the 1364-1995 syntax and the above is the *addition* of a second
opening "(" before the outputs.


Here is a concrete example showing each of the above three syntaxes.

specify
( posedge in => out : data ) ) = 1; // 1364-1995 syntax
( posedge in => out : data ) = 1; // 1364-2001 syntax
( posedge in => ( out : data ) ) = 1; // syntax required by Verilog-XL, NC-Verilog and MTI
endspecify


Dennis Marsa
Xilinx, Inc.
Fix
In Syntax 14-4 and in A.7.4, the syntax of parallel_edge_sensitive_path_description
and full_edge_sensitive_path_description should be corrected as follows:

CHANGE

parallel_edge_sensitive_path_description ::= 
        "(" [ edge_identifier ] specify_input_terminal_descriptor "=>" 
        specify_output_terminal_descriptor [ polarity_operator ] ":" data_source_expression ")" 

TO 

parallel_edge_sensitive_path_description ::= 
        "(" [ edge_identifier ] specify_input_terminal_descriptor "=>" 
        "(" specify_output_terminal_descriptor [ polarity_operator ] ":" data_source_expression ")" ")" 

and

CHANGE

full_edge_sensitive_path_description ::= 
        "(" [ edge_identifier ] list_of_path_inputs "*>" 
        list_of_path_outputs [ polarity_operator ] ":" data_source_expression ")" 

TO

full_edge_sensitive_path_description ::= 
        "(" [ edge_identifier ] list_of_path_inputs "*>" 
        "(" list_of_path_outputs [ polarity_operator ] ":" data_source_expression ")" ")" 



The quotation marks around a symbol in the above mean it should be in bold font.

In both cases, the correction is an extra pair of parentheses around the outputs.
Audit-Trail

From: Shalom Bresticker <Shalom.Bresticker@motorola.com>
To: Dennis Marsa <drm@xilinx.com>
Cc: etf-bugs@boyd.com
Subject: Re: errata/338: syntax of edge sensitive module path descriptions
Date: Thu, 01 May 2003 17:48:26 +0300

It seems to me that your third syntax always was and is the correct syntax.

If you look at the examples on the page following the syntax boxes you reference,
in both 1995 and 2001, you will find the extra left parenthesis there.

You will also find the error pointed out way back in
http://boydtechinc.com/btf/archive/btf_1997/1210.html .

I don't know how and why a right parenthesis was deleted instead.

Unformatted



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