| Number | 334
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| Category | errata
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| Synopsis | 12.7, Example 2: incorrect comment "redundant assignments to reg r"
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| State | lrmdraft
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| Class | errata-discuss
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| Arrival-Date | Apr 27 2003
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| Originator | Shalom.Bresticker@motorola.com
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| Release | 2001b: 12.6, Example 2
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| Environment |
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| Description |
In 12.6, Example 2, there is a comment, "// redundant assignments to reg r". I see only one assignment, and it does not look redundant. I don't have 1364-1995 with me for comparison. |
| Fix |
12.7 Example 2 is almost completely incorrect. So CHANGE Example 2-The following example shows an incompletely defined downward reference that can be accessed. task t; reg r, s; begin : b t.b.r = 0; // poorly defined but found by upward search t.s = 0; // fully defined downward reference end endtask TO Example 2-The following example shows how variables can be accessed directly or with hierarchical names. task t; reg s; begin : b reg r; t.b.r = 0; // These three lines access the same variable r b.r = 0; r = 0; t.s = 0; // These two lines access the same variable s s = 0; end endtask |
| Audit-Trail |
From: Steven Sharp <sharp@cadence.com> To: etf-bugs@boyd.com, Shalom.Bresticker@motorola.com Cc: Subject: Re: errata/334: 12.6, Example 2: incorrect comment "redundant assignments to reg r"? Date: Mon, 28 Apr 2003 21:12:01 -0400 (EDT) This is not the only issue with this example. There is a reference to t.b.r, but r is not declared inside block b. The name appears to be invalid, not just poorly defined. If r were declared inside block b or the reference were changed to t.r, the reference would be valid. In either of these cases, I don't see how this is any more "poorly defined but found by upward search" than the t.s reference after it, which is labelled as "fully defined downward reference." Steven Sharp sharp@cadence.com From: Shalom Bresticker <Shalom.Bresticker@motorola.com> To: Steven Sharp <sharp@cadence.com> Cc: etf-bugs@boyd.com Subject: Re: errata/334: 12.6, Example 2: incorrect comment "redundant assignments to reg r"? Date: Wed, 30 Apr 2003 10:17:55 +0300 > This is not the only issue with this example. There is a reference to > t.b.r, but r is not declared inside block b. The name appears to be > invalid, not just poorly defined. You are correct. I had assumed, without checking that it works, that the intention was to say that the search goes upwards to t, downwards to b, and then back up to find r. But you are right, it does not work. I checked in Verilog-XL. > If r were declared inside block b > or the reference were changed to t.r, the reference would be valid. > In either of these cases, I don't see how this is any more "poorly > defined but found by upward search" than the t.s reference after it, > which is labelled as "fully defined downward reference." And t.s is not a downward reference, either. By the way, this example exists with no change in 1364-1995, also. But I do now understand the source of the reference to "redundant assignments". I looked in the Cadence Verilog-XL Reference Manual (end of Chapter 11). This section has also not changed from 1995 till now. There the example looks as follows: task t; reg r; begin :b // redundant assignments to reg r t.b.r = 0; // this is poorly defined but can find r by an upward search t.r = 0; // this is a fully defined downward reference end endtask So originally there WERE two assignments to r. But as you say, the reference to t.b.r still does not work. You should pass that on to your documentation department. Shalom Fix replaced by Shalom.Bresticker@freescale.com on Sun Nov 28 06:35:28 2004 12.7 Example 2 is almost completely incorrect. So CHANGE Example 2-The following example shows an incompletely defined downward reference that can be accessed. task t; reg r, s; begin : b t.b.r = 0; // poorly defined but found by upward search t.s = 0; // fully defined downward reference end endtask TO Example 2-The following example shows how variables can be accessed directly or with hierarchical names. task t; reg s; begin : b reg r; t.b.r = 0; // These three lines access the same variable r b.r = 0; r = 0; t.s = 0; // These two lines access the same variable s s = 0; end endtask |
| Unformatted |
reg r"? |
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