| Number | 299
|
| Category | errata
|
| Synopsis | /117 comments
|
| State | closed
|
| Class | mistaken
|
| Arrival-Date | Mar 10 2003
|
| Originator | Steven Sharp <sharp@cadence.com>
|
| Release | 2001b
|
| Environment |
|
| Description |
I did some investigation of the questions in part 3. Verilog-XL doesn't care about pairing of the `celldefine/`endcelldefine directives. There can be multiple `celldefine directives in a row, and multiple `endcelldefines in a row or before any `celldefines. NC-Verilog is similarly forgiving, and I checked what it does with the directives. The behavior appears to be that `celldefine turns on the tagging (whether it was on before or not), and `endcelldefine turns off the tagging (whether it was on before or not). Steven Sharp sharp@cadence.com |
| Fix |
comments were supposed to go into 117... |
| Audit-Trail |
|
| Unformatted |
|
Hosted by Boyd Technology