| Add Proposal | Add Analysis | Edit Class, Environment, or Release |
| Number | 234
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| Category | errata
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| Synopsis | 12.3.{2,3,6}, named port connections for implicit ports with same name
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| State | open
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| Class | errata-discuss
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| Arrival-Date | Dec 25 2002
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| Originator | "Brad Pierce" <Brad.Pierce@synopsys.com>
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| Release | 2001b: 12.3
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| Environment |
204,227,233,234,292,332,345,452 |
| Description |
According to section 12.3.2 -- "Use of named port connections shall not be used for implicit ports unless the port_expression is a simple port_identifier." Could an instance of a module like same_input() from 12.3.3 be connected by name? -- module same_input (a,a); input a; // This is legal. The inputs are tied together. ... For example, by same_input inst(.a(io1)); Also, is it legal for explicit ports to have the same name, for example, -- module same_input2 (.p(a),.p(a)); input a; or module same_input3 (.p(a),.p(b)); ... (In same_input3, a and b might even be of different sizes.) -- Brad |
| Fix |
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| Audit-Trail |
From: "James A. Markevitch" <jam@magic.com> To: etf-bugs@boyd.com Cc: Subject: Re: errata/234: 12.3.{2,3,6}, named port connections for implicit ports with same name Date: Sun, 30 Nov 2003 18:50:49 -0800 (PST) The comments below are intended to discuss legal syntax. Once that has been generally agreed upon, I will write the proposed changes to the text. Vendors: how do existing tools handle the "same_input" and "same_input2" cases below? > According to section 12.3.2 -- > > "Use of named port connections shall not be used for implicit > ports unless the port_expression is a simple port_identifier." > > Could an instance of a module like same_input() from 12.3.3 be > connected by name? -- > > module same_input (a,a); > input a; // This is legal. The inputs are tied together. > ... This is legal. This is the Verilog 1995 syntax. > For example, by > > same_input inst(.a(io1)); This should be legal, in either Verilog 1995 or Verilog 2001. Do existing tools accept this? > Also, is it legal for explicit ports to have the same name, > for example, -- > > module same_input2 (.p(a),.p(a)); > input a; How do existing tools deal with this? Technically, this might be legal. But, the expressions would need to be identical (unless one actually allowed equivalence between things like {a,{b,c}} and {{a,b},c} ... yuck). > or > module same_input3 (.p(a),.p(b)); > ... Illegal. The intent of multiple occurrences of the same name in the port list is that the identical signal is connected to multiple ports. > (In same_input3, a and b might even be of different sizes.) > > -- Brad James Markevitch From: Shalom Bresticker <Shalom.Bresticker@motorola.com> To: etf-bugs@boyd.com Cc: Subject: Re: errata/234: Re: errata/234: 12.3.{2,3,6}, named port connections for implicit ports with same name Date: Mon, 01 Dec 2003 14:43:31 +0200 > Vendors: how do existing tools handle the "same_input" and "same_input2" > cases below? > > > According to section 12.3.2 -- > > > > "Use of named port connections shall not be used for implicit > > ports unless the port_expression is a simple port_identifier." > > > > Could an instance of a module like same_input() from 12.3.3 be > > connected by name? -- > > > > module same_input (a,a); > > input a; // This is legal. The inputs are tied together. > > ... > > This is legal. This is the Verilog 1995 syntax. > > > For example, by > > > > same_input inst(.a(io1)); > > This should be legal, in either Verilog 1995 or Verilog 2001. > > Do existing tools accept this? Verilog-XL and NC-Verilog issue a warning about "Too few module port connections". The VCS compiler does not. > > Also, is it legal for explicit ports to have the same name, > > for example, -- > > > > module same_input2 (.p(a),.p(a)); > > input a; > > How do existing tools deal with this? Technically, this might be legal. > But, the expressions would need to be identical (unless one actually > allowed equivalence between things like {a,{b,c}} and {{a,b},c} ... yuck). Verilog-XL and NC-Verilog issue errors about "Port name previously declared". So does VCS. > > or > > module same_input3 (.p(a),.p(b)); > > ... > > Illegal. The intent of multiple occurrences of the same name in the > port list is that the identical signal is connected to multiple ports. Same response as previous case, obviously. -- Shalom Bresticker Shalom.Bresticker@motorola.com Design & Reuse Methodology Tel: +972 9 9522268 Motorola Semiconductor Israel, Ltd. Fax: +972 9 9522890 POB 2208, Herzlia 46120, ISRAEL Cell: +972 50 441478 |
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