It's mostly a lot of little picky stuff, but still ...

Let's start with what I'm more or less sure of:

- In the instantiation of sms_16b216t0, "...rasb" should be ".rasb",
"...dqi" should be ".dqi".

- In the instantiation of sms_16b208t0, "...rasb" should be ".rasb",
"...dev_id" should be ".dev_id".

- In the instantiation of sms_16b208t0, i should run from 0 to 7.

I'm less sure of the rest, since I am not familiar with DIMMs.

The example seems to be incomplete, which I do not like.

I think examples in standards documents should contain all needed
details.

Adam, I think these examples originated with you.

Can you check these details ?  Thanks.

- input adr is [11:0], but only [10:0] are used in both instantiations.

- input ds[7:0] is not used at all.

- Is clk really [3:0] ?

- wires rasb, casb, csb, web, bex[7:0] are not used at all.

- The 8M 16b wide mem is called sms_16b216t0,

while the 16M 8b wide mem is called sms_16b208t0.

Is that correct? What's the naming convention ?

- devid3[4:0] and devid7[4:0] are undeclared.

- The input adr to dimm is 12b wide, whereas the input address to task
read_mem is 32b wide.

- Task read_mem appears to call a task with the same name which is apparently
defined within the sms modules, but not shown. The use of the same task
name for both is confusing.

 

 

-- 
**************************************************************************
Shalom Bresticker                           Shalom.Bresticker@motorola.com
Motorola Semiconductor Israel, Ltd.                  Tel #: +972 9 9522268
P.O.B. 2208, Herzlia 46120, ISRAEL                   Fax #: +972 9 9522890
**************************************************************************

module dimm (adr, ba, rasx, casx, csx, wex, dqm, cke, data, clk,
dev_id);
  parameter [31:0] MEM_SIZE  = 8,  // in mbytes
                   MEM_WIDTH = 16;
  input [10:0] adr;
  input        ba;
  input        rasx, casx, csx, wex;
  input [ 7:0] dqm;
  input        cke;
  inout [63:0] data;
  input        clk;
  input [ 4:0] dev_id;

  genvar       i;

  generate
    case ({MEM_SIZE, MEM_WIDTH})
      {32'd8, 32'd16}: // 8Meg x 16 bits wide.
      begin
        // The generated instance names are word[3].p, word[2].p,
        // word[1].p, word[0].p, and the task read_mem
        for (i=0; i<4; i=i+1) begin:word
          sms_16b216t0 p (.clk(clk), .csb(csx), .cke(cke),
              .ba(ba[0]), .addr(adr[10:0]), .rasb(rasx), 
              .casb(casx), .web(wex), .udqm(dqm[2*i+1]), 
              .ldqm(dqm[2*i]), .dqi(data[15+16*i:16*i]), 
              .dev_id(dev_id[4:0]));
        end
        task read_mem;
          input  [31:0] address;
          output [63:0] data;
          begin
            word[3].p.read_mem(address, data[63:48]);
            word[2].p.read_mem(address, data[47:32]);
            word[1].p.read_mem(address, data[31:16]);
            word[0].p.read_mem(address, data[15:0]);
          end
        endtask
      end
      
      {32'd16, 32'd8}: // 16Meg x 8 bits wide.
        begin
          // The generated instance names are byte[7].p,
	  byte[6].p,
          // byte[5].p, byte[4].p, byte[3].p, byte[2].p,
	  byte[1].p,
          // byte[0].p and the task read_mem
          for (i=0; i<8; i=i+1) begin:byte
            sms_16b208t0 p (.clk(clk), .csb(csx), .cke(cke),
                .ba(ba[0]), .addr(adr[10:0]), .rasb(rasx), 
                .casb(casx), .web(wex), .dqm(dqm[i]), 
                .dqi(data[7+8*i:8*i]),.dev_id(dev_id[4:0]));
          end
          task read_mem;
            input  [31:0] address;
            output [63:0] data;
            begin
              byte[7].p.read_mem(address, data[63:56]);
              byte[6].p.read_mem(address, data[55:48]);
              byte[5].p.read_mem(address, data[47:40]);
              byte[4].p.read_mem(address, data[39:32]);
              byte[3].p.read_mem(address, data[31:24]);
              byte[2].p.read_mem(address, data[23:16]);
              byte[1].p.read_mem(address, data[15:8]);
              byte[0].p.read_mem(address, data[7:0]);
            end
          endtask
        end
      // Other memory cases ...
    endcase
  endgenerate
endmodule