| Add Proposal | Add Analysis | Edit Class, Environment, or Release |
| Number | 99
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| Category | errata
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| Synopsis | Annex B: include, incdir, library listed as reserved
|
| State | open
|
| Class | errata-discuss
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| Arrival-Date | Aug 17 2002
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| Originator | sharp@cadence.com
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| Release | 2001b: Annex B
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| Environment |
http://boydtechinc.com/etf/archive/etf_2002/0011.html |
| Description |
Annex B lists "include", "incdir" and "library" as keywords. As far as I know, these are not keywords in Verilog source. They are only keywords in library mapping files. I don't think they should be listed as keywords, which implies they are disallowed as identifiers in Verilog source. See earlier mail message: http://boydtechinc.com/etf/archive/etf_2002/0011.html |
| Fix |
I think these should be removed from Annex B, or that Annex B needs to document keywords in Verilog source separately from keywords in other related files (such as library map files and VCD files). |
| Audit-Trail |
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| Unformatted |
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