| Add Proposal | Add Analysis | Edit Class, Environment, or Release |
| Number | 385
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| Category | enhancement
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| Synopsis | interconnect net that resolves to type
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| State | open
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| Class | enhancement
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| Arrival-Date | Jul 09 2003
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| Originator | sharp@cadence.com
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| Release | 2001b
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| Environment |
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| Description |
This is a request from my Verilog-AMS contact. All I have is the description in the synopsis above. With what little I can tell from that, I may not approve of this being added to Verilog. It sounds like something that calls for deferring the determination of information about a net until it is known what it is connected to. Verilog already does too much deferring of things until elaboration, and it causes inefficient compilation. Clearly we would need a more detailed description. This is just a placeholder for the request. |
| Fix |
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| Audit-Trail |
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| Unformatted |
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