From: Paul Graham (firstname.lastname@example.org)
Date: Tue Dec 11 2001 - 10:40:47 PST
Consider this example:
module m(q, d1, d2);
output [7:0] q;
input signed [7:0] d1, d2;
assign q = d1 && d2;
Since operands d1 and d2 are signed, the result of (d1 && d2) should be
signed, correct? Furthermore the result is one bit wide. So it must be
sign extended before assignment to q. If the result is 1'b1, then with sign
extension it will be 8'b11111111.
Yet that is not how verilog-xl does it. verilog-xl apparently treats the
result of a logical operator as an unsigned bit. This makes perfect sense
to me, but it appears to violate the lrm. It seems that the result of a
logical operation should always be considered unsigned.
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