From: Paul Graham (email@example.com)
Date: Thu Nov 29 2001 - 21:46:04 PST
> I do not understant this. There are many places even in Verilog 95 such
> as UDP parsing that require completely different rules. Scanner and parser
> generators (lex, yacc, etc.) always have "subroutine" mechanisms for
> exactly this situation. Are you saying that V2K Verilog must emit syntax
> error for use of "keyword" cell anywhere and it is not compliant with
> V2k to only recognize cell in configuration section?
The LRM gives a list of predefined keywords, including the keyword "cell".
It does not say that certain identifiers are keywords in certain contexts
and not in others.
Context sensitivity would have to be defined for each keyword. For
instance, the keyword "end" *could* be used as a normal identifier anywhere
outside of a begin/end block without ambiguity. Or "always" could be an
identifier within procedural block without ambiguity (since "always" can
only be a keyword in the context of a module item). In theory, a lexer
could be set up to parse something like this:
output reg begin;
always @(begin or end)
begin : blah
When you mention UDP lexer subroutines, perhaps you mean parsing of table
entries, where number-like constructs are intepreted very differently from
ordinary numbers. I'm not aware of any keywords used in a UDP that can be
declared as identifiers in a module, or vice versa.
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