From: Don Mills (mills@lcdm-eng.com)
Date: Mon Sep 10 2001 - 21:25:14 PDT
I have did not have a chance to respond to this email earlier. There have
already been a number of postings today regarding your questions and various
responses. I must acknowledge that I do have an error in my paper as has
been noted and clarified by Stu.
In answer to your question below and to indicate acknowledgment of needed
clarification let me try to correct myself. As I understand this syntax
(via discussions with both Stu and Cliff) and as Stu iterated in one of his
responses earlier this evening, any signal connected to a port of a module
can be implicitly declared. This means "connected to a port of the
containing module". All internal undeclared internal signals will default
to scalar wire - including signals on the left-hand side of a continuous
assignment statement (Verilog 2001) and signals "connected to a port of an
instantiated module" even if the signal inside the instantiated module was a
vector (Verilog 1995).
In other words, if I want an internal wire (a wire that is not connected to
a port of the module) that is to be a vector, it must be explicitly declared
or it will default to scalar.
I apologize for the confusion and error in the paper.
The paragraph should have read something like this:
<p> 3.19 Implicit nets with continuous assignments
Verilog-1995 will infer a net data type for an undeclared signal on
the left-hand side of a continuous assignment only if the signal
name is also connected to a port of that module. If the signal is
not connected to a port of that module, then Verilog-1995 considers the
signal as
undeclared. Verilog-2000 extends the implicit net declaration to
include any signal on the left-hand side of a continuous
assignment. If the signal is connected to a module port of the
module, then the implicit net will default to the vector width of
the port. If the signal is not connected to a port, then it will
default to scalar and truncate all bits from the expression on the
right-hand side
of the assignment except for the lsb. The lsb of the right-hand side
being assigned to the implicit wire scalar signal on the left-hand side of
the assignment.
Paul Graham wrote:
> My name is Paul Graham. I work in the Ambit group at Cadence. I was
> reading your paper called "Getting the most out of the Verilog-2000
> standard" and I was puzzled by the section on implicit net declarations:
>
> 3.19 Implicit nets with continuous assignments
>
> Verilog-1995 will infer a net data type for an undeclared signal on
> the left-hand side of a continuous assignment only if the signal
> name is also connected to a port of that module. If the signal is
> not connected to a port, the Verilog-1995 considers the signal as
> undeclared. Verilog-2000 extends the implicit net declaration to
> include any signal on the left-hand side of a continuous
> assignment. If the signal is connected to a module port of the
> module, then the implicit net will default to the vector width of
> the port. If the signal is not connected to a port, the it will
> default to the vector width of the expression on the right-hand side
> of the assignment.
>
> You say that if a signal is connected to a port of a module, then it
> can be implicitly declared. Do you mean connected to a port of the
> containing module, or connected to a port of an instantiated module?
>
> module m(q, a, b, c, d);
> ...
>
> // connected to a port of the containing module
> tmp = d;
>
> // connected to a port of an instantiated module
> and(tmp, a, b, c);
>
> I assume you mean the second case.
>
> Also, does Verilog-2000 say that an implicitly declared signal can be
> more than one bit wide? I don't see any support for this in the
> Verilog-2000 LRM. I also don't see any support for an implicit
> declaration of the target of an assignment. Section 3.5 only lists
> port expressions and connections to modules and primitives.
>
> Paul
-- ========================================================== Don Mills LCDM Engineering (Logic, Coding, & Design Methodology) mills@lcdm-eng.com www.lcdm-eng.com 801-282-6560 Office PHONE 801-641-5882 Mobile PHONE 4158 W. Ben Armine Cir., South Jordan, UT 84095-9101 ==========================================================
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