Re: implicit nets

From: Paul Graham (pgraham@cadence.com)
Date: Tue Jul 31 2001 - 11:14:06 PDT


Shalom,

The wording of section 6.1.2 was updated to refer to section 3.5, which is
good, sort of. It is good that the definition of an implicit signal was
concentrated in one section in the LRM, instead of being repeated
redundantly in several sections. But 3.5, the key section, was never
updated to include the new intention of allowing an assignment lhs to imply
an implicit signal declaration.

Section 6.1.2 is also inaccurate, in that it suggests that an assignment
target may *only* be an explicitly or implicitly declared net. It can of
course be a part-select or bit-select or concatenation.

Or what about:

    parameter p1 = 4, p2 = 4;
    input [p1-1:0] x, y;

    assign z = x * y;

What is the width of z? Is it 1? Is it (p1 + p2)?

Since the LRM has been through several drafts and has been approved by the
IEEE with the existing wording, and since this new type of implicit
declaration has some unresolved issues, I think that Verilog-2001 should
omit this new feature. Let it go into Verilog-2006, after it has been
thought through more carefully.

Paul

> I think you are half right.
>
> Section 6.1.2 says,
> "The continuous assignment statement shall place a continuous assignment on a net data type. The net may be explicitly declared, or
> may inherit an implicit declaration in accordance with the implicit declarations rules defined in 3.5."
>
> Unfortunately, section 3.5 does not mention that case.
>
> I'll file a bug report.
>
> What should the width be in that case ?
> According to my mail archives, it seems that a scalar is created unless the name is connected to a vector port.
>
> Shalom
>
>
> Paul Graham wrote:
>
> > Looking at Stuart Sutherland's Verilog-2000 presentation, I see a section
> > called "Default Nets with Continuous Assigns". It says there that if the
> > target of a continuous assignment is an undeclared name, then an implicit
> > wire declaration of the appropriate width will be created. I don't see
> > any reference to this rule in the LRM itself. Am I missing something?



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