From: Pragmatic C Software (sjmeyer@pragmatic-c.com)
Date: Mon Jul 30 2001 - 19:42:46 PDT
I think I must be missing something but I have always assumed that use
before declaration was allowed in Verilog (also 1995 P1364) because
implicit wire declarations and parameter overrides (aka defparams) require
two passes anyway. Hasn't something like this always been legal?
module xx(a[p1], a[p2], a[p3]);
output [16:0] a;
parameter p1 = 1;
paramter p2 = 2;
paramter p3 = 3;
initial $display("p4=%s", p4);
paramter p4 = "a string";
endmodule
<p><p>Quoting Stefen Boyd (stefen@boyd.com):
> Precedence: bulk
>
> At 11:08 AM 7/26/2001 -0700, Michael McNamara wrote:
> >We did discuss this, and at one point there was a proposal that one
> >could have parameter declarations inside the port list, and that these
> >parameters would be the only ones that were overridable:
>
> Mac,
>
> Steven and I had a brief interchange regarding this
> that didn't make it out to the reflector:
>
> At 03:08 PM 7/26/2001 -0400, you wrote:
> > >I vaguely remember talking about this... we
> > >were considering adding parameter declarations
> > >into the ansi style module declarations. I
> > >guess that got dropped on the floor.
> >
> >They got added in, mixed in with the ports, which was ugly. We changed
> >this to put them all before the ports in a separate #(...) construct. This
> >matches the syntax of the instantiation with parameter overrides. And since
> >they come before the port declarations, they can be used there.
> >
> >However, that only covers parameters, not localparams.
> >
> >Steven Sharp
>
> We put an example in 12.2 using the module parameter
> list. I guess it would have been nice to have allowed
> localparam in this list...
>
> Stefen
>
>
> --------------------
> Stefen Boyd Boyd Technology, Inc.
> stefen@BoydTechInc.com (408)739-BOYD
> www.BoydTechInc.com (408)739-1402 (fax)
>
-- Steve Meyer sjmeyer@pragmatic-c.com
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