From: Steven Sharp (firstname.lastname@example.org)
Date: Thu Jul 19 2001 - 12:35:58 PDT
>> That's far too vague. For instance, an array of regs can be referenced
>> using a variable index. Surely this is not allowed for an array of
>Why not ?
All references in Verilog must have a bit length known at compile time.
This is not a problem with a variable index into an array of regs, since
all of the elements have the same bit width. However, objects in different
elements of an array of modules can have different bit widths, since they
can be declared using parameters which are subject to parameter overrides.
Therefore, a reference to an object in an array of instances using a
variable index would not have a constant known width.
This would be even worse when generate-if was implemented, since a name
could reference completely different kinds of objects in different instances.
For example, instance.foo could be a reg, while instance.foo could
be a task, and instance.foo could be a module instance.
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