From: Paul Graham (pgraham@cadence.com)
Date: Mon Jul 09 2001 - 12:48:05 PDT
> I am curious.
>
> Is Verilog-XL thinking that the parameter in a function
> is interpreted as if it appears in the enclosing module?
> What if there are two functions with the same parameter declaration within
> it?
>
> If not, how is the hierarchical name for the parameter in the function
> specified in a defparam statement?
Sorry for starting this. I should have checked the reference manual,
that is, I should have run Verilog-XL, before asking my original question.
The answer is, yes, a function or task can have a parameter, and the parameter
lives in the scope of the function or task:
module m...
function f;
parameter p = 1;
...
endfunction
defparam f.p = 2;
assign q2 = f(x);
endmodule
<p>Paul
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