From: Shalom Bresticker (Shalom.Bresticker@motorola.com)
Date: Wed Mar 14 2001 - 01:12:55 PST
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Michael,
<p>5.6.6 in 1364-1995 describes a different situation.
<p>5.6.6 describes one internal signal which is connected to two external
ports.
<br>I asked about one external port which is connected to two internal
signals.
<p>By the way, the example in 5.6.6 was moved to 12.3.3.
<p>Shalom
<br>
<p>Michael McNamara wrote:
<blockquote TYPE=CITE>Shalom Bresticker writes:
<br> >
<br> > The following question came up on comp.lang.verilog.
<br> >
<br> > I am not sure of the answer and did not find explicit mention
in 1364.
<br> >
<br> > Is "module qq ( .v(a), .v(b) )" legal, and if so, what does
it do ?
<br> >
<br> > (External port name is v. Internal nets/variables a and b are
connected to it.)
<br>
<p>The 'Section 5.6.6 Port Connections'
<p>has described this exact situation, since 1364-1995 came out.
<p>Actually, there the example is module foo(.a(p), .b(p));
<p>Yes, 5.6.6 is the wrong place, and there was some discussion of moving
<br>this to section 12, but I have no access to the ballot version so I
<br>don't know if this was done.</blockquote>
<pre>--
**************************************************************************
Shalom Bresticker Shalom.Bresticker@motorola.com
Motorola Semiconductor Israel, Ltd. Tel #: +972 9 9522268
P.O.B. 2208, Herzlia 46120, ISRAEL Fax #: +972 9 9522890
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