From: Michael McNamara (mac@verisity.com)
Date: Mon Nov 13 2000 - 08:22:25 PST
Stu, you are correct, that the BNF is in error.
Essentially, two proposals met and crashed. One had us doing better
ports for modules; another had us adding port lists to tasks and
functions.
I will create correct BNF and send it to the BTF by the end of today.
<p>Stuart Sutherland writes:
> BTF,
>
> I received the following concern regarding the BNF and the new combined
> port/type declarations.
>
> Stu
>
> >From: Dhiraj Raj <draj@cupertino.synopsys.com>
> >Date: Wed, 8 Nov 2000 11:59:56 -0800 (PST)
> >To: stuart@sutherland-hdl.com
> >Subject: task/function port declarations
> >X-Sun-Charset: US-ASCII
> >
> >I am a bit confused here.
> >
> >On Pages 764 and 765, the grammar for Verilog 2000 is
> >
> >there is input_declaration in the function rules. And input_declaration,
> >output_declaration and inout_declaration in the task rules. So these rules
> >will allow something like this...
> >
> >task;
> >input wire a;
> >begin
> >end
> >endtask
> >
> >Interestingly the grammar doesn't allow this.
> >
> >task(input a);
> >wire a;
> >begin
> >end
> >endtask
> >
> >Also the following is not allowed in the current language.
> >Declaring a wire in a task is a syntax error.
> >
> >task;
> >input a;
> >wire a;
> >begin
> >end
> >endtask
> >
> >So shouldn't input_declaration for tasks/functions be replaced by just
> >"input list_of_port_identifiers" and the same for output_declaration and
> >inout_declaration.
> >
> >Any comments?
> >
> >Thanks
> >Dhiraj
>
> ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> Stuart Sutherland Sutherland HDL Inc.
> stuart@sutherland-hdl.com 22805 SW 92nd Place
> phone: 503-692-0898 Tualatin, OR 97062
> www.sutherland-hdl.com
> ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
>
>
>
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