From: Vivek Sagdeo (vsagdeo@best.com)
Date: Sun Aug 17 1997 - 17:52:49 PDT
The abstract of original proposal is :
Abstract: Verilog tasks currently are not re-entrant. Many engineers do
not even know the problem exists. Currently, each task call uses the
ame registers used by previous calls to the same task, even if the task
was already invoked and is currently running; therefore, existing task
variables become overwritten.
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This wa discssed in the conference call last week and an alternate method
of supporting the capability of reentrant tasks was suggested by
Karen Pieper using 'automatic' variable declarations.
The variables declared with n 'auto' prefix would get stacked on each
invocation like in "C". This provides the capability equivalent to
static and automatic variables in a programming language like "C".
Vivek supported this idea suggesting the added benefit of hardware
design using these features with clarifiaction of the original intent
of the task feature. "synthesizability" (either via tools or basic
ability to map the HDL description into hardware) was the reason.
Tasks are to belooked at modeling a pipelined design whereby the same resources
ces get used again and again on separate invocations of the task.
However, stackable variable s can also be synthesized but are to be declared
-d as such using the 'auto' declaration.
Thus, from hardware description as welll as test-bench generation with the
"C" like capbilities, additon of 'auto' prefix to declaration within a
task will provide many more capabilities and solve several problems with
finer control for the re-entrant tasks.
Vivek
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