Date: Fri May 09 1997 - 13:42:49 PDT
1) Note: one needs a signed modulus operator as well.
2) Verilog already has typed data: the unsigned type, the real type,
and the integer type. Would you have us remove these existing
types? Replacing integer with just a reg [31:0] and then using the
signed operators when needed, works fine, but:
Replacing real with reg [63:0], and using new real operators
requires for + - * / % < <= >= > ==, and = as well. (it also would
potentially allow appling real operations on objects of size other
than REAL*8, albeit if this was interesting, we could just and a
range to the real type
3) Another large use for Verilog (other than the two you pointed out
of specifing hardware, and of prototyping hardware) is writing
testbenchs for hardware; and I submit, this is the spot where
signed and real types are of the most use.
4) using ` prefix for signed operators is perhaps the easiest in terms
of jamming this feature into the language; it by no means is
obvious or elegant. The ` tells me these operators are DIFFERENT;
but doesn't tell me why or in what way. To a new user it will be
confusing. With the added requirement that we need new operators
for real, one needs to get even more creative. `s< and `r< perhaps?
So while it is definately an intriguing proposal, I am afraid that
since it is a rather radical change to the language, one which is
incompatible with existing integer and real types, that I am leaning
against this proposal.
However, let the discussion continue!
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